workonebeta.tan.rpt

Verilog实现的DDS正弦信号发生器和测频测相模块

; Type                         ; Slack                                    ; Required Time ; Actual Time                                    ; From                                   ; To                                                                                                                                           ; From Clock ; To Clock  ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+----------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+------------+-----------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; 5.772 ns                                       ; Increase                               ; Adjust:AdjustU0|rSetPhase[0]                                                                                                                 ; --         ; SysClock  ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 15.607 ns                                      ; PhasaeLeadJudge                        ; LeadFlag                                                                                                                                     ; WaveInTwo  ; --        ; 0            ;
; Worst-case tpd               ; N/A                                      ; None          ; 4.995 ns                                       ; SysClock                               ; ClockOut                                                                                                                                     ; --         ; --        ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 6.689 ns                                       ; WaveInOne                              ; PhasaeLeadJudge                                                                                                                              ; --         ; WaveInTwo ; 0            ;
; Clock Setup: 'SysClock'      ; N/A                                      ; None          ; 115.77 MHz ( period = 8.638 ns )               ; Adjust:AdjustU0|rSetFrequency[4]       ; Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component|altsyncram_fp21:auto_generated|ram_block1a9~porta_address_reg4 ; SysClock   ; SysClock  ; 0            ;
; Clock Setup: 'ReadClock'     ; N/A                                      ; None          ; 127.62 MHz ( period = 7.836 ns )               ; Read:ReadU0|Counter[4]                 ; Read:ReadU0|tempbit                                                                                                                          ; ReadClock  ; ReadClock ; 0            ;
; Clock Setup: 'WaveInOne'     ; N/A                                      ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Measure:MeasureU0|rPhaseWaveCounter[0] ; Measure:MeasureU0|rPhaseWaveCounter[31]                                                                                                      ; WaveInOne  ; WaveInOne ; 0            ;
; Clock Setup: 'WaveInTwo'     ; N/A                                      ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Measure:MeasureU0|rPhaseWaveCounter[0] ; Measure:MeasureU0|rPhaseWaveCounter[31]                                                                                                      ; WaveInTwo  ; WaveInTwo ; 0            ;
; Clock Hold: 'SysClock'       ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; Measure:MeasureU0|rFreClockCounter[30] ; Read:ReadU0|SourceData[94]                                                                                                                   ; SysClock   ; SysClock  ; 64           ;
; Total number of failed paths ;                                          ;               ;                                                ;                                        ;                                                                                                                                              ;            ;           ; 64           ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+----------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+------------+-----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; SysClock        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ReadClock       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;