_primary.vhd

来自「高速FIFO」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity test is
    generic(
        IDLE            : integer := 0;
        WRITE           : integer := 1;
        READ            : integer := 3;
        SAME            : integer := 5;
        WRITE2          : integer := 4;
        RANDOM          : integer := 7;
        READ2           : integer := 2
    );
end test;