m3s058ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Block Repeat Controller Latches
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.001

// Revision history
// V1.001 - 29 July 1996
//          RdBRCR added.

// m3s058ct
// M320C50 Latches for use with the block repeat controller.
// These latches, together with the MemCycle control line are in a
// separate block to prevent the synthesiser from mixing MemCycle with
// the decoding logic.

module m3s058ct (Clock, MemCycle, NextPASR, NextPAER, NextBRCR, NextRdBRCR,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
  PASR, PAER, BRCR, RdBRCR);

    input         Clock, MemCycle;
    input  [15:0] NextPASR, NextPAER, NextBRCR, NextRdBRCR;
    output [15:0] PASR, PAER, BRCR, RdBRCR;

    reg [15:0] PASR, PAER, BRCR, RdBRCR;


always @(posedge Clock)
if (MemCycle)
begin
    PASR <= NextPASR;
    PAER <= NextPAER;
    BRCR <= NextBRCR;
    RdBRCR <= NextRdBRCR;
end

endmodule