m3s078ct.v
来自「这是16位定点dsp源代码。已仿真和综合过了」· Verilog 代码 · 共 112 行
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112 行
//******************************************************************* ////IMPORTANT NOTICE ////================ ////Copyright Mentor Graphics Corporation 1996 - 1998. All rights reserved. ////This file and associated deliverables are the trade secrets, ////confidential information and copyrighted works of Mentor Graphics ////Corporation and its licensors and are subject to your license agreement ////with Mentor Graphics Corporation. //// ////These deliverables may be used for the purpose of making silicon for one ////IC design only. No further use of these deliverables for the purpose of ////making silicon from an IC design is permitted without the payment of an ////additional license fee. See your license agreement with Mentor Graphics ////for further details. If you have further questions please contact ////Mentor Graphics Customer Support. //// ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on ////workstation hostid 800059c1 Inventra //// Pre-Scaler// Copyright Mentor Graphics Corporation and Licensors 1998. // V1.001// m3s078ct.v// M320C50 ALU pre-scaler, 16-bits in, 32-bits out.//// Cntrl usage:// 0 : Shift left 16// 1 : Shift left 16 with rounding (ZALR)// 2 : Suppress sign extensionmodule m3s078ct (ScalerOp, ScalerIp, Shift, Cntrl, SXM);//******************************************************************* ////IMPORTANT NOTICE ////================ ////Copyright Mentor Graphics Corporation 1996 - 1998. All rights reserved. ////This file and associated deliverables are the trade secrets, ////confidential information and copyrighted works of Mentor Graphics ////Corporation and its licensors and are subject to your license agreement ////with Mentor Graphics Corporation. //// ////These deliverables may be used for the purpose of making silicon for one ////IC design only. No further use of these deliverables for the purpose of ////making silicon from an IC design is permitted without the payment of an ////additional license fee. See your license agreement with Mentor Graphics ////for further details. If you have further questions please contact ////Mentor Graphics Customer Support. //// ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on ////workstation hostid 800059c1 Inventra // input [15:0] ScalerIp; input [3:0] Shift; input [2:0] Cntrl; input SXM; output [31:0] ScalerOp; reg [7:0] SignExtn; reg [31:0] ScalerOp;// Generate sign extension bits from SXM and input bit 15always @(Cntrl or SXM or ScalerIp) if (SXM & ScalerIp[15] & ~Cntrl[2]) SignExtn = 8'hFF; else SignExtn = 8'b0;always @(ScalerIp or Shift or SignExtn or Cntrl)begin if (Cntrl[0]) ScalerOp = {ScalerIp,Cntrl[1],15'b0}; else begin if (Shift[0]) ScalerOp = {ScalerIp[15:0],1'b0}; else ScalerOp = {SignExtn[0],ScalerIp[15:0]}; if (Shift[1]) ScalerOp = {ScalerOp[16:0],2'b0}; else ScalerOp = {SignExtn[1:0],ScalerOp[16:0]}; if (Shift[2]) ScalerOp = {ScalerOp[18:0],4'b0}; else ScalerOp = {SignExtn[3:0],ScalerOp[18:0]}; if (Shift[3]) ScalerOp = {ScalerOp[22:0],8'b0}; else ScalerOp = {SignExtn[7:0],ScalerOp[22:0]}; ScalerOp = {SignExtn[0],ScalerOp[30:0]}; endend endmodule⌨️ 快捷键说明
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