ram01_control.v

来自「这是16位定点dsp源代码。已仿真和综合过了」· Verilog 代码 · 共 85 行

module RAM01_Control (NSCE,SRNW,SAWA,NSWE,NSOE,SPND,SAPA,SARA,IOD,q01,address01,data01,PD01,SD01,wren01);

input  [5-1:0] NSCE,SRNW,NSWE,NSOE,SPND;
input  [14:0] SAWA,SAPA,SARA;
input  [15:0] IOD,q01;
output  [10:0] address01;
output  [15:0] data01,PD01,SD01;
output  wren01;

reg  [15:0] iPSD,iSD;
reg  [15:0] idata01;
reg  iwren01;
reg  [10:0] iaddress01;
reg  [15:0] PD01,SD01;
reg  [15:0] data01;
reg  wren01;
reg  [10:0] address01;

always @(SARA or SAWA or SAPA or SPND or SRNW or
         IOD or SPND or NSWE or NSOE or q01)
 begin
  if (!NSWE[1] & !SRNW[1])
   begin 
    iaddress01 = SAWA[10:0];
    idata01 = IOD;
    iwren01 = ~NSWE[1];
   end
  else
   begin 
    iaddress01 = 11'bz;
    idata01 = 16'bz;
    iwren01 = 1'bz;
   end

  if (SPND[1])
   begin
    iPSD = q01;
    iSD = q01;
    if (!NSOE[1] & SRNW[1])
     begin
      iaddress01 = SAPA[10:0];      
     end
    else
     begin
      iaddress01 = 11'bz; 
     end
   end
  else
   begin
    iPSD = 16'bz;
    iSD = 16'bz;
    if (!NSOE[1] & SRNW[1]) 
     begin
      iaddress01 = SARA[10:0];
     end
    else
     begin
      iaddress01 = 11'bz; 
     end
   end
 end
   

always @(NSCE or iPSD or iSD or idata01 or iwren01 or iaddress01)
 begin
  if (!NSCE[1])
   begin
    PD01 = iPSD;
    SD01 = iSD;
    data01 = idata01;
    wren01 = iwren01;
    address01 = iaddress01;
   end
  else
   begin
    PD01 = 16'bz;
    SD01 = 16'bz;
    data01 = 16'bz;
    wren01 = 1'bz;
    address01 = 11'bz;
   end
 end
   
endmodule