ram00_control.v

来自「这是16位定点dsp源代码。已仿真和综合过了」· Verilog 代码 · 共 85 行

module RAM00_Control (NSCE,SRNW,SAWA,NSWE,NSOE,SPND,SAPA,SARA,IOD,q00,address00,data00,PD00,SD00,wren00);

input  [5-1:0] NSCE,SRNW,NSWE,NSOE,SPND;
input  [14:0] SAWA,SAPA,SARA;
input  [15:0] IOD,q00;
output  [10:0] address00;
output  [15:0] data00,PD00,SD00;
output  wren00;

reg  [15:0] iPSD,iSD;
reg  [15:0] idata00;
reg  iwren00;
reg  [10:0] iaddress00;
reg  [15:0] PD00,SD00;
reg  [15:0] data00;
reg  wren00;
reg  [10:0] address00;

always @(SARA or SAWA or SAPA or SPND or SRNW or
         IOD or SPND or NSWE or NSOE or q00)
 begin
  if (!NSWE[0] & !SRNW[0])
   begin 
    iaddress00 = SAWA[10:0];
    idata00 = IOD;
    iwren00 = ~NSWE[0];
   end
  else
   begin 
    iaddress00 = 11'bz;
    idata00 = 16'bz;
    iwren00 = 1'bz;
   end

  if (SPND[0])
   begin
    iPSD = q00;
    iSD = q00;
    if (!NSOE[0] & SRNW[0])
     begin
      iaddress00 = SAPA[10:0];      
     end
    else
     begin
      iaddress00 = 11'bz; 
     end
   end
  else
   begin
    iPSD = 16'bz;
    iSD = 16'bz;
    if (!NSOE[0] & SRNW[0]) 
     begin
      iaddress00 = SARA[10:0];
     end
    else
     begin
      iaddress00 = 11'bz; 
     end
   end
 end
   

always @(NSCE or iPSD or iSD or idata00 or iwren00 or iaddress00)
 begin
  if (!NSCE[0])
   begin
    PD00 = iPSD;
    SD00 = iSD;
    data00 = idata00;
    wren00 = iwren00;
    address00 = iaddress00;
   end
  else
   begin
    PD00 = 16'bz;
    SD00 = 16'bz;
    data00 = 16'bz;
    wren00 = 1'bz;
    address00 = 11'bz;
   end
 end
   
endmodule