tms320c50.v

来自「这是16位定点dsp源代码。已仿真和综合过了」· Verilog 代码 · 共 94 行

module tms320c50 (READY,NHOLD,NBIO,NINT1,NINT2,NINT3,NINT4,NMI,NRS,MPNMC,
CLKMD1,CLKMD2,CLKIN1,CLKR,TCLKR,DR,TDR,CLKIN2,FSR,TCK,TDI,
TMS,TRST,EMU0,EMU1,NDS_O,NPS_O,NIS_O,NRD_O,NWR_O,NHOLDA,NIAQ,XF,NIACK,
CLKOUT1,X1,TOUT,DX_O,TDX_O,TDO,A,D,RNW,NSTB,NBR_O,CLKX,TCLKX,TFSR,FSX,TFSX,CLKRAM);

input READY,NHOLD,NBIO,CLKRAM;
input NINT1,NINT2,NINT3,NINT4;
input NMI,NRS,MPNMC;
input CLKMD1,CLKMD2;//unuse
input CLKIN1,CLKR,TCLKR,DR,TDR;
input CLKIN2;//unuse
input FSR;
input TCK,TDI;//unuse
input TMS,TRST,EMU0,EMU1;//unuse

output NDS_O,NPS_O,NIS_O,NRD_O,NWR_O;
output NHOLDA,NIAQ,XF,NIACK;
output CLKOUT1,X1,TOUT,DX_O,TDX_O;
output TDO;

inout [15:0] A,D;
inout RNW,NSTB,NBR_O;
inout CLKX,TCLKX;
inout TFSR,FSX,TFSX;

wire READY,NHOLD,NBIO,CLKRAM;
wire NINT1,NINT2,NINT3,NINT4;
wire NMI,NRS,MPNMC;
wire CLKMD1,CLKMD2;//unuse
wire CLKIN1,CLKR,TCLKR,DR,TDR;
wire CLKIN2;//unuse
wire FSR;
wire TCK,TDI;//unuse
wire TMS,TRST,EMU0,EMU1;//unuse

wire NDS_O,NPS_O,NIS_O,NRD_O,NWR_O;
wire NHOLDA,NIAQ,XF,NIACK;
wire CLKOUT1,X1,TOUT,DX_O,TDX_O;
wire TDO;

wire [15:0] A,D;
wire RNW,NSTB,NRB_O;
wire CLKX,TCLKX;
wire TFSR,FSX,TFSX;

wire         NCLKI, NBRI;
wire         NNMI;
wire  [15:0] DI, PD, B0D, B1D, B2D, SD, PD_O, SD_O;
wire  [14:0] AI;
wire         PRdy, SRdy, RNWI, NSTRBI;
wire         CLKXI, TCLKXI;
wire         FSXI, TFSXI;
wire        CLKO, CLKXO, NCLKXE, TCLKXO, NTCLKXE;
wire        NHLDA, NHOE, IDLE2, RNWO, NSTRBO;
wire [14:0] PA, SARA, SAWA, SAPA;
wire [8:0]  B0WA, B0RA, WA, RA;
wire [2:0]  NBWR, NBRD;
wire        NPCE, NPOE, NPWE;
wire [15:0] OA, OD, IOD;
wire [5-1:0] SRNW, SPND, NSCE, NSWE, NSOE;
wire        NDEN, NPS, NDS, NIS, NWR, NRD, NBR;
wire        DX, NDXE, TDX, NTDXE, FSXO, NFSXE, TFSXO, NTFSXE;
wire        TADD, NTADDE, NBR_O;


assign NHOLDA = NHLDA;
assign NSTRBI = NSTB;
assign PD = PD_O;
assign SD = SD_O;
m3s000ct U1 (DI, READY, NRS, NCLKI, MPNMC, NBIO, NHOLD, NBRI,
NNMI, NINT1, NINT2, NINT3, NINT4,
B0D, B1D, B2D, PD, SD, SRdy, PRdy, AI, RNWI, NSTRBI,
OA, IOD, OD, NDEN, NBR, NDS, NPS, NIS, NRD, NWR, XF, CLKO,
CLKXI, CLKR, TCLKXI, TCLKR,
DR, TDR, FSR, FSXI, TFSR, TFSXI,
CLKXO, NCLKXE, TCLKXO, NTCLKXE, TOUT, NIAQ, NHLDA, NHOE, IDLE2, NIACK,
DX, NDXE, TDX, NTDXE, FSXO, NFSXE, TFSXO, NTFSXE, TADD, NTADDE,
NBRD, NBWR, RA, WA, B0RA, B0WA,
PA, NPCE, NPWE, NPOE, SARA, SAWA, SAPA, SRNW, SPND, NSCE, NSWE, NSOE,
RNWO, NSTRBO);

mc50_control U2 (NRD, NWR, NDS, NPS, NIS,
CLKIN1,NCLKI,NHOE,NRD_O,NWR_O,NDS_O,NPS_O,NIS_O,
OA,A,AI,NDEN,OD,RNW,RNWO,RNWI,NSTB,NBR_O,NBR,NBRI,
NCLKXE,CLKX,CLKXO,CLKXI,NTCLKXE, TCLKXO, TCLKX,TCLKXI,NDXE,DX,DX_O,
NTDXE, TDX,TDX_O,NTADDE, TADD, TFSR,NFSXE, FSXO, FSX,FSXI,
NTFSXE, TFSXO, TFSX,TFSXI,X1,DI,D,NSTRBO,NNMI,NMI,CLKO,CLKOUT1,
TDO,SRdy,PRdy);

mc50mem U3 (IOD,B0WA,B0RA,WA,RA,NBWR,NBRD,B0D,B1D,B2D,
NSCE,SRNW,SAWA,NSWE,NSOE,SPND,SAPA,SARA,PD_O,SD_O,
NPCE,NPOE,NPWE,PA,CLKRAM);

endmodule