tms320c50_pll.v

这是16位定点dsp源代码。已仿真和综合过了

module tms320c50_PLL (READY,NHOLD,NBIO,NINT1,NINT2,NINT3,NINT4,NMI,NRS,MPNMC,
CLKMD1,CLKMD2,CLKR,TCLKR,DR,TDR,CLKIN2,FSR,TCK,TDI,
TMS,TRST,EMU0,EMU1,NDS_O,NPS_O,NIS_O,NRD_O,NWR_O,NHOLDA,NIAQ,XF,NIACK,
CLKOUT1,X1,TOUT,DX_O,TDX_O,TDO,A,D,RNW,NSTB,NBR_O,CLKX,TCLKX,TFSR,FSX,TFSX,CLK);

input READY,NHOLD,NBIO,CLK;
input NINT1,NINT2,NINT3,NINT4;
input NMI,NRS,MPNMC;
input CLKMD1,CLKMD2;//unuse
input CLKR,TCLKR,DR,TDR;
input CLKIN2;//unuse
input FSR;
input TCK,TDI;//unuse
input TMS,TRST,EMU0,EMU1;//unuse

output NDS_O,NPS_O,NIS_O,NRD_O,NWR_O;
output NHOLDA,NIAQ,XF,NIACK;
output CLKOUT1,X1,TOUT,DX_O,TDX_O;
output TDO;

inout [15:0] A,D;
inout RNW,NSTB,NBR_O;
inout CLKX,TCLKX;
inout TFSR,FSX,TFSX;

wire READY,NHOLD,NBIO,CLK;
wire NINT1,NINT2,NINT3,NINT4;
wire NMI,NRS,MPNMC;
wire CLKMD1,CLKMD2;//unuse
wire CLKR,TCLKR,DR,TDR;
wire CLKIN2;//unuse
wire FSR;
wire TCK,TDI;//unuse
wire TMS,TRST,EMU0,EMU1;//unuse

wire NDS_O,NPS_O,NIS_O,NRD_O,NWR_O;
wire NHOLDA,NIAQ,XF,NIACK;
wire CLKOUT1,X1,TOUT,DX_O,TDX_O;
wire TDO;

wire [15:0] A,D;
wire RNW,NSTB,NRB_O;
wire CLKX,TCLKX;
wire TFSR,FSX,TFSX;

wire         NCLKI, NBRI;
wire         NNMI;
wire  [15:0] DI, PD, B0D, B1D, B2D, SD, PD_O, SD_O;
wire  [14:0] AI;
wire         PRdy, SRdy, RNWI, NSTRBI;
wire         CLKXI, TCLKXI;
wire         FSXI, TFSXI;
wire        CLKO, CLKXO, NCLKXE, TCLKXO, NTCLKXE;
wire        NHLDA, NHOE, IDLE2, RNWO, NSTRBO;
wire [14:0] PA, SARA, SAWA, SAPA;
wire [8:0]  B0WA, B0RA, WA, RA;
wire [2:0]  NBWR, NBRD;
wire        NPCE, NPOE, NPWE;
wire [15:0] OA, OD, IOD;
wire [5-1:0] SRNW, SPND, NSCE, NSWE, NSOE;
wire        NDEN, NPS, NDS, NIS, NWR, NRD, NBR;
wire        DX, NDXE, TDX, NTDXE, FSXO, NFSXE, TFSXO, NTFSXE;
wire        TADD, NTADDE, NBR_O;

tms320c50 U1 (READY,NHOLD,NBIO,NINT1,NINT2,NINT3,NINT4,NMI,NRS,MPNMC,
CLKMD1,CLKMD2,CLKIN1,CLKR,TCLKR,DR,TDR,CLKIN2,FSR,TCK,TDI,
TMS,TRST,EMU0,EMU1,NDS_O,NPS_O,NIS_O,NRD_O,NWR_O,NHOLDA,NIAQ,XF,NIACK,
CLKOUT1,X1,TOUT,DX_O,TDX_O,TDO,A,D,RNW,NSTB,NBR_O,CLKX,TCLKX,TFSR,FSX,TFSX,CLKRAM);

PLL1 U2 (CLK,CLKRAM,CLKIN1);

endmodule