ram02_control.v

来自「这是16位定点dsp源代码。已仿真和综合过了」· Verilog 代码 · 共 85 行

module RAM02_Control (NSCE,SRNW,SAWA,NSWE,NSOE,SPND,SAPA,SARA,IOD,q02,address02,data02,PD02,SD02,wren02);

input  [5-1:0] NSCE,SRNW,NSWE,NSOE,SPND;
input  [14:0] SAWA,SAPA,SARA;
input  [15:0] IOD,q02;
output  [10:0] address02;
output  [15:0] data02,PD02,SD02;
output  wren02;

reg  [15:0] iPSD,iSD;
reg  [15:0] idata02;
reg  iwren02;
reg  [10:0] iaddress02;
reg  [15:0] PD02,SD02;
reg  [15:0] data02;
reg  wren02;
reg  [10:0] address02;

always @(SARA or SAWA or SAPA or SPND or SRNW or
         IOD or SPND or NSWE or NSOE or q02)
 begin
  if (!NSWE[2] & !SRNW[2])
   begin 
    iaddress02 = SAWA[10:0];
    idata02 = IOD;
    iwren02 = ~NSWE[2];
   end
  else
   begin 
    iaddress02 = 11'bz;
    idata02 = 16'bz;
    iwren02 = 1'bz;
   end

  if (SPND[2])
   begin
    iPSD = q02;
    iSD = q02;
    if (!NSOE[2] & SRNW[2])
     begin
      iaddress02 = SAPA[10:0];      
     end
    else
     begin
      iaddress02 = 11'bz; 
     end
   end
  else
   begin
    iPSD = 16'bz;
    iSD = 16'bz;
    if (!NSOE[2] & SRNW[2]) 
     begin
      iaddress02 = SARA[10:0];
     end
    else
     begin
      iaddress02 = 11'bz; 
     end
   end
 end
   

always @(NSCE or iPSD or iSD or idata02 or iwren02 or iaddress02)
 begin
  if (!NSCE[2])
   begin
    PD02 = iPSD;
    SD02 = iSD;
    data02 = idata02;
    wren02 = iwren02;
    address02 = iaddress02;
   end
  else
   begin
    PD02 = 16'bz;
    SD02 = 16'bz;
    data02 = 16'bz;
    wren02 = 1'bz;
    address02 = 11'bz;
   end
 end
   
endmodule