ram03_control.v

来自「这是16位定点dsp源代码。已仿真和综合过了」· Verilog 代码 · 共 85 行

module RAM03_Control (NSCE,SRNW,SAWA,NSWE,NSOE,SPND,SAPA,SARA,IOD,q03,address03,data03,PD03,SD03,wren03);

input  [5-1:0] NSCE,SRNW,NSWE,NSOE,SPND;
input  [14:0] SAWA,SAPA,SARA;
input  [15:0] IOD,q03;
output  [10:0] address03;
output  [15:0] data03,PD03,SD03;
output  wren03;

reg  [15:0] iPSD,iSD;
reg  [15:0] idata03;
reg  iwren03;
reg  [10:0] iaddress03;
reg  [15:0] PD03,SD03;
reg  [15:0] data03;
reg  wren03;
reg  [10:0] address03;

always @(SARA or SAWA or SAPA or SPND or SRNW or
         IOD or SPND or NSWE or NSOE or q03)
 begin
  if (!NSWE[3] & !SRNW[3])
   begin 
    iaddress03 = SAWA[10:0];
    idata03 = IOD;
    iwren03 = ~NSWE[3];
   end
  else
   begin 
    iaddress03 = 11'bz;
    idata03 = 16'bz;
    iwren03 = 1'bz;
   end

  if (SPND[3])
   begin
    iPSD = q03;
    iSD = q03;
    if (!NSOE[3] & SRNW[3])
     begin
      iaddress03 = SAPA[10:0];      
     end
    else
     begin
      iaddress03 = 11'bz; 
     end
   end
  else
   begin
    iPSD = 16'bz;
    iSD = 16'bz;
    if (!NSOE[3] & SRNW[3]) 
     begin
      iaddress03 = SARA[10:0];
     end
    else
     begin
      iaddress03 = 11'bz; 
     end
   end
 end
   

always @(NSCE or iPSD or iSD or idata03 or iwren03 or iaddress03)
 begin
  if (!NSCE[3])
   begin
    PD03 = iPSD;
    SD03 = iSD;
    data03 = idata03;
    wren03 = iwren03;
    address03 = iaddress03;
   end
  else
   begin
    PD03 = 16'bz;
    SD03 = 16'bz;
    data03 = 16'bz;
    wren03 = 1'bz;
    address03 = 11'bz;
   end
 end
   
endmodule