latch000.v

来自「这是16位定点dsp源代码。已仿真和综合过了」· Verilog 代码 · 共 17 行

module latch000 (RNW,D,A,D_O,A_O);

 input [15:0] D,A;
 input RNW;
 output [15:0] D_O,A_O;
 
 wire RNW;
 wire [15:0] A,D;
 reg  [15:0] A_O,D_O;

  always @(A or D or RNW)
   if (RNW)
    begin
     A_O = A;
     D_O = ~D;
    end
endmodule