i2c_slave.v

一个好用的经过FPGA验证的i2c_slave verilog代码。

				addr_in_state  <= addr_in5;
		end				
		addr_in4:
		begin
			if({scl_regi0,scl_regi,scl}==3'b011)
			begin
				addr_in_state  <= addr_in3;
				addr_in_reg[4] <= sda_in;
			end
			else
				addr_in_state  <= addr_in4;
		end				
		addr_in3:
		begin
			if({scl_regi0,scl_regi,scl}==3'b011)
			begin
				addr_in_state  <= addr_in2;
				addr_in_reg[3] <= sda_in;
			end
			else
				addr_in_state  <= addr_in3;
		end			
		addr_in2:
		begin
			if({scl_regi0,scl_regi,scl}==3'b011)
			begin
				addr_in_state  <= addr_in1;
				addr_in_reg[2] <= sda_in;
			end
			else
				addr_in_state  <= addr_in2;
		end				
		addr_in1:
		begin
			if({scl_regi0,scl_regi,scl}==3'b011)
			begin
				addr_in_state  <= addr_in0;
				addr_in_reg[1] <= sda_in;
			end
			else
				addr_in_state  <= addr_in1;
		end				
		addr_in0:
		begin
			if({scl_regi0,scl_regi,scl}==3'b011)
			begin
				addr_in_state  <= addr_end;
				addr_in_reg[0] <= sda_in;
			end
			else
				addr_in_state <= addr_in0;		    
		end
		addr_end:	addr_in_state <= addr_in6;
		default:	addr_in_state <= addr_in6;
		endcase
	end
	else
		addr_in_state  <= addr_in6;  

//------------------------------------------------------------------	
//to read data from master
 
always @(posedge clock or negedge reset_n2)
	if(!reset_n2)
	begin
		data_in_state <= data_in7;
     
		data_in_reg1  <= 8'b00001010;  //vgf
		data_in_reg0  <= 8'b01000000;  //bdl
		
		data_reg1     <= 8'b00001010;  //vgf
		data_reg0     <= 8'b01000000;  //bdl
	end
	else
	begin
		if(main_state==data_write)
			case(data_in_state)	
			data_in7:
			begin	 
				if({scl_regi0,scl_regi,scl}==3'b011)          
				begin	
					case(reg_addr)
					8'haa:	data_in_reg0[7] <= sda_in; 
					8'h55:	data_in_reg1[7] <= sda_in;
					endcase								    
					data_in_state <= data_in6;                             
				end
				else
					data_in_state <= data_in7; 
			end	
			data_in6:
			begin	
				if({scl_regi0,scl_regi,scl}==3'b011)
				begin					     
					case(reg_addr)
					8'haa:	data_in_reg0[6] <= sda_in; 
					8'h55:	data_in_reg1[6] <= sda_in;
					endcase			
					data_in_state <= data_in5;
				end
				else
					data_in_state <= data_in6; 
			end
			data_in5:
			begin	
				if({scl_regi0,scl_regi,scl}==3'b011)
				begin					     
					data_in_state <= data_in4;
					case(reg_addr)
					8'haa:	data_in_reg0[5] <= sda_in; 
					8'h55:	data_in_reg1[5] <= sda_in;
					endcase
				end
				else
					data_in_state <= data_in5;     			
			end	
						
			data_in4:
			begin	
				if({scl_regi0,scl_regi,scl}==3'b011)  	
				begin				    
					data_in_state <= data_in3;
					case(reg_addr)
					8'haa:	data_in_reg0[4] <= sda_in; 
					8'h55:data_in_reg1[4] <= sda_in;
					endcase	
				end	
				else
					data_in_state <= data_in4;    	
			end
					
			data_in3: 
			begin	
				if({scl_regi0,scl_regi,scl}==3'b011)  
				begin					    
					data_in_state <= data_in2;
					case(reg_addr)
					8'haa:	data_in_reg0[3] <= sda_in; 
					8'h55:	data_in_reg1[3] <= sda_in;
					endcase	
				end	
				else
					data_in_state <= data_in3;  	
			end
					
			data_in2:			 
			begin		
				if({scl_regi0,scl_regi,scl}==3'b011)  
				begin				  
					case(reg_addr)
					8'haa:	data_in_reg0[2] <= sda_in; 
					8'h55:	data_in_reg1[2] <= sda_in;
					endcase			
					data_in_state <= data_in1;
				end
				else
					data_in_state <= data_in2; 
			end
								
			data_in1:
			begin
				if({scl_regi0,scl_regi,scl}==3'b011)   
				begin
					data_in_state <= data_in0;
					case(reg_addr)
					8'haa:	data_in_reg0[1] <= sda_in; 
					8'h55:	data_in_reg1[1] <= sda_in;
					endcase
				end	
				else
					data_in_state <= data_in1;   		
			end
							
			data_in0:
			begin
				if({scl_regi0,scl_regi,scl}==3'b011) 
				begin
					data_in_state <= data_end;
					case(reg_addr)
					8'haa:	data_in_reg0[0] <= sda_in; 
					8'h55:	data_in_reg1[0] <= sda_in;
					endcase
				end	
				else
					data_in_state <= data_in0;   						    
			end 
					     
			data_end:
			begin
				case(reg_addr)
				8'haa:	data_reg0 <= data_in_reg0; 
				8'h55:	data_reg1 <= data_in_reg1;
				endcase
				data_in_state <= data_in7;
			end
			default: data_in_state <= data_in7;
			endcase
		else
			data_in_state <= data_in7;     
	end

//------------------------------------------------------------------	
//to read register addr from master

always @(posedge clock or negedge reset_n2)
begin
	if(!reset_n2)
	begin
		reg_addr       <= 8'b0000_0000;
		reg_addr_state <= reg_addr7; 
	end
	else
	begin
		if(main_state==reg_addr_read)
			case(reg_addr_state)	
			reg_addr7:
			begin	 
				if({scl_regi0,scl_regi,scl}==3'b011)          
				begin	
					reg_addr[7]    <= sda_in;          			    
					reg_addr_state <= reg_addr6;                             
				end
				else
					reg_addr_state <= reg_addr7; 
			end	
			reg_addr6:
			begin	
				if({scl_regi0,scl_regi,scl}==3'b011)
				begin					     
					reg_addr[6]    <= sda_in; 
					reg_addr_state <= reg_addr5;
				end
				else
					reg_addr_state <= reg_addr6; 
			end
			reg_addr5:
			begin	
				if({scl_regi0,scl_regi,scl}==3'b011)
				begin	
					reg_addr[5]    <= sda_in;				     
					reg_addr_state <= reg_addr4;						                      
				end
				else
					reg_addr_state <= reg_addr5;     			
			end	
			reg_addr4:
			begin	
				if({scl_regi0,scl_regi,scl}==3'b011)  	
				begin				    
					reg_addr_state <= reg_addr3;
					reg_addr[4]    <= sda_in;             
				end	
				else
					reg_addr_state <= reg_addr4;    	
			end
			reg_addr3: 
			begin	
				if({scl_regi0,scl_regi,scl}==3'b011)  
				begin					    
					reg_addr_state <= reg_addr2;
					reg_addr[3]    <= sda_in;          
				end	
				else
					reg_addr_state <= reg_addr3;  	
			end
			reg_addr2:			 
			begin		
				if({scl_regi0,scl_regi,scl}==3'b011)  
				begin				  
					reg_addr[2]    <= sda_in;           
					reg_addr_state <= reg_addr1;
				end
				else
					reg_addr_state <= reg_addr2; 
			end
			reg_addr1:
			begin
				if({scl_regi0,scl_regi,scl}==3'b011)   
				begin
					reg_addr_state <= reg_addr0;
					reg_addr[1]    <= sda_in;           
				end	
				else
					reg_addr_state <= reg_addr1;   		
			end
			reg_addr0:
			begin
				if({scl_regi0,scl_regi,scl}==3'b011) 
				begin
					reg_addr_state <= reg_addr_end;
					reg_addr[0]    <= sda_in;      
				end	
				else
					reg_addr_state<= reg_addr0;   						    
			end 
			reg_addr_end:
			begin
				reg_addr_state  <= reg_addr7;
			end                        
			default: reg_addr_state <= reg_addr7;
			endcase
		else
			reg_addr_state <= reg_addr7;     
	end
end

//---------------------to read data in task--------------------------------
 
always@(posedge clock or negedge reset_n2) //data read
	if(!reset_n2)
	begin
		data_out_state <= data_out7;
		sda_out2       <= 1'b0;   
	end
	else
	begin   
		case(data_out_state)
		data_out7:
		begin			                    
			if(main_state==data_read&&{scl_regi0,scl_regi,scl}==3'b100)
			begin		                          
				case(reg_addr)
				8'haa:	sda_out2 <= data_in_reg0[7]; 
				8'h55:	sda_out2 <= data_in_reg1[7];
				endcase             
				data_out_state   <= data_out6;					                         
			end                         
			else                        
			begin                       
				data_out_state   <= data_out7; 
			end  
		end 
		data_out6:
		begin
			if({scl_regi0,scl_regi,scl}==3'b100)
			begin
				data_out_state   <= data_out5;
			                            
				case(reg_addr)      
				8'haa:	sda_out2 <= data_in_reg0[6]; 
				8'h55:	sda_out2 <= data_in_reg1[6];
				endcase	            
			end                         
			else                        
				data_out_state   <= data_out6;		
		end
		data_out5:
		begin
			if({scl_regi0,scl_regi,scl}==3'b100)
			begin
				data_out_state   <= data_out4;		                          
				case(reg_addr)      
				8'haa:	sda_out2 <= data_in_reg0[5]; 
				8'h55:	sda_out2 <= data_in_reg1[5];
				endcase			 
			end                         
			else                        
				data_out_state   <= data_out5; 
		end
		data_out4:
		begin
			if({scl_regi0,scl_regi,scl}==3'b100)
			begin
				data_out_state   <= data_out3;			                          
				case(reg_addr)      
				8'haa:	sda_out2 <= data_in_reg0[4]; 
				8'h55:	sda_out2 <= data_in_reg1[4];
				endcase             
			end	                    
			else                        
				data_out_state   <= data_out4; 		
		end
		data_out3:
		begin
			if({scl_regi0,scl_regi,scl}==3'b100)
			begin
				data_out_state   <= data_out2;		                          
				case(reg_addr)      
				8'haa:	sda_out2 <= data_in_reg0[3]; 
				8'h55:	sda_out2 <= data_in_reg1[3];
				endcase             
			end	                    
			else                        
				data_out_state   <= data_out3; 		
		end
		data_out2:
		begin
			if({scl_regi0,scl_regi,scl}==3'b100) 
			begin
				data_out_state   <= data_out1;			                          
				case(reg_addr)
				8'haa:	sda_out2 <= data_in_reg0[2]; 
				8'h55:	sda_out2 <= data_in_reg1[2];				 
				endcase             
			end                         
			else                        
				data_out_state   <= data_out2; 			
		end
		data_out1:
		begin
			if({scl_regi0,scl_regi,scl}==3'b100)
			begin
				data_out_state   <= data_out0;		                          
				case(reg_addr)
				8'haa:	sda_out2 <= data_in_reg0[1]; 
				8'h55:	sda_out2 <= data_in_reg1[1];
				endcase	
			end	
			else
				data_out_state   <=data_out1; 	
		end
		data_out0:
		begin
			if({scl_regi0,scl_regi,scl}==3'b100)
			begin  
				data_out_state   <= data_out_end;
				case(reg_addr)
				8'haa:	sda_out2 <= data_in_reg0[0]; 
				8'h55:	sda_out2 <= data_in_reg1[0];
				endcase
			end
			else
				data_out_state   <= data_out0;
			  			
		end
		data_out_end:
		begin
			if({scl_regi0,scl_regi,scl}==3'b100)
				data_out_state <= data_out7;
			else                      
				data_out_state <= data_out_end; 
		end                               
			                          
		default:	data_out_state <= data_out7;
		endcase	     
	end
 
endmodule