i2c_slave_top.v

一个好用的经过FPGA验证的i2c_slave verilog代码。

`timescale	1ns/1ps

module i2c_slave_top(
	reset_n,
	sda,
	scl,
	clock, 
	data_in_reg0,   
        data_in_reg1,
        clock_signalTap
	);
	
input		reset_n;	//extern signal
input		scl;
inout		sda;	
input		clock;		//intern signal

output	[7:0]	data_in_reg0;	//to define eight register 
output	[7:0]	data_in_reg1;
output		clock_signalTap;

reg	[3:0] 	count;
wire 		clock0;

always@(posedge clock)
	if(!reset_n)		//??2
		count <= 4'b0;
	else
		count <= count + 1'b1;


assign clock_signalTap = count[3];
assign clock0          = count[2];
    
wire sda_en;
wire sda_in;
wire sda_out;
    
assign  sda_in = (!sda_en) ? sda  : 1'bz;
assign	sda    = sda_en ? sda_out : 1'bz;

i2c_slave	i2c_slave_inst(
			.reset_n(reset_n),
			.clock(clock0),
			.sda_out(sda_out),
			.sda_in(sda_in),
			.sda_en(sda_en),
			.scl(scl),
			.data_reg0(data_in_reg0),   
			.data_reg1(data_in_reg1)
                            );
	
endmodule