📄 keypadscan.cxt
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<!ELEMENT XorMux (IPort)><!ATTLIST XorMux Nm CDATA #REQUIRED><!ELEMENT FbMux (IPort)><!ATTLIST FbMux Nm CDATA #REQUIRED><!ELEMENT OutBuf (IPort, OPort, CntlPort*)><!ATTLIST OutBuf Nm CDATA #REQUIRED IOS (LVTTL | LVCMOS15 | LVCMOS18 | LVCMOS25 | LVCMOS33 | HSTL_I | SSTL2_I | SSTL3_I | STRIG) #REQUIRED><!ELEMENT DFlop (FlopPort+)><!ATTLIST DFlop Nm CDATA #REQUIRED><!ELEMENT FlopPort EMPTY><!ATTLIST FlopPort NNm CDATA #REQUIRED Port (D | CLK | Q | RST | PST | CE) #REQUIRED><!ELEMENT IPort EMPTY><!ATTLIST IPort NNm CDATA #REQUIRED><!ELEMENT OPort EMPTY><!ATTLIST OPort NNm CDATA #REQUIRED><!ELEMENT CntlPort EMPTY><!ATTLIST CntlPort NNm CDATA #REQUIRED>]>
<Document Date="Mar 04 13:07:32 2005" Device="XC2C32A-6CP56" Module="KeypadScan" Version="2"><Net IoT="out" Loc="FB1_9" NNm="out<0>" SNm="out<0>"/><Net IoT="out" Loc="FB1_1" NNm="row<0>" SNm="row<0>"/><Net IoT="out" Loc="FB2_1" NNm="out<1>" SNm="out<1>"/><Net IoT="out" Loc="FB1_2" NNm="row<1>" SNm="row<1>"/><Net IoT="out" Loc="FB2_2" NNm="out<2>" SNm="out<2>"/><Net IoT="out" Loc="FB1_3" NNm="row<2>" SNm="row<2>"/><Net IoT="out" Loc="FB2_3" NNm="out<3>" SNm="out<3>"/><Net IoT="out" Loc="FB1_4" NNm="row<3>" SNm="row<3>"/><Net IoT="out" Loc="FB2_4" NNm="out<4>" SNm="out<4>"/><Net IoT="out" Loc="FB1_5" NNm="row<4>" SNm="row<4>"/><Net IoT="out" Loc="FB2_6" NNm="out<5>" SNm="out<5>"/><Net IoT="out" Loc="FB1_6" NNm="row<5>" SNm="row<5>"/><Net IoT="out" Loc="FB1_7" NNm="row<6>" SNm="row<6>"/><Net IoT="out" Loc="FB1_8" NNm="row<7>" SNm="row<7>"/><Net IoT="none" NNm="FB1_PT10" SNm="FB1_PT10"/><Net IoT="none" NNm="FB1_PT11" SNm="FB1_PT11"/><Net IoT="none" NNm="FB1_PT20" SNm="FB1_PT20"/><Net IoT="none" NNm="FB2_PT10" SNm="FB2_PT10"/><Net IoT="none" NNm="FB1_PT12" SNm="FB1_PT12"/><Net IoT="none" NNm="FB1_PT21" SNm="FB1_PT21"/><Net IoT="none" NNm="FB1_PT30" SNm="FB1_PT30"/><Net IoT="none" NNm="FB2_PT11" SNm="FB2_PT11"/><Net IoT="none" NNm="FB1_PT13" SNm="FB1_PT13"/><Net IoT="none" NNm="FB1_PT22" SNm="FB1_PT22"/><Net IoT="none" NNm="FB1_PT31" SNm="FB1_PT31"/><Net IoT="none" NNm="FB2_PT12" SNm="FB2_PT12"/><Net IoT="none" NNm="FB1_PT14" SNm="FB1_PT14"/><Net IoT="none" NNm="FB1_PT23" SNm="FB1_PT23"/><Net IoT="none" NNm="FB1_PT32" SNm="FB1_PT32"/><Net IoT="none" NNm="FB2_PT13" SNm="FB2_PT13"/><Net IoT="none" NNm="FB1_PT15" SNm="FB1_PT15"/><Net IoT="none" NNm="FB1_PT24" SNm="FB1_PT24"/><Net IoT="none" NNm="FB1_PT16" SNm="FB1_PT16"/><Net IoT="none" NNm="FB1_PT25" SNm="FB1_PT25"/><Net IoT="none" NNm="FB1_PT52" SNm="N_PZ_98"/><Net IoT="none" NNm="FB1_PT17" SNm="FB1_PT17"/><Net IoT="none" NNm="FB1_PT26" SNm="FB1_PT26"/><Net IoT="none" NNm="FB1_PT18" SNm="FB1_PT18"/><Net IoT="none" NNm="FB1_PT27" SNm="FB1_PT27"/><Net IoT="none" NNm="FB1_PT19" SNm="FB1_PT19"/><Net IoT="none" NNm="FB1_PT28" SNm="FB1_PT28"/><Net IoT="none" NNm="FB1_PT55" SNm="N_PZ_96"/><Net IoT="none" NNm="FB1_PT29" SNm="FB1_PT29"/><Net IoT="in" Loc="FB2_5" NNm="clk" SNm="clk" ClkT="G"/><Net IoT="in" Loc="FB1_10" NNm="column<0>" SNm="column<0>"/><Net IoT="in" Loc="FB1_11" NNm="column<1>" SNm="column<1>"/><Net IoT="in" Loc="FB1_12" NNm="column<2>" SNm="column<2>"/><Net IoT="in" Loc="FB1_13" NNm="column<3>" SNm="column<3>"/><Net IoT="in" Loc="FB1_14" NNm="column<4>" SNm="column<4>"/><Net IoT="in" Loc="FB1_15" NNm="column<5>" SNm="column<5>"/><Net IoT="in" Loc="FB1_16" NNm="column<6>" SNm="column<6>"/><Net IoT="in" Loc="FB2_7" NNm="column<7>" SNm="column<7>"/><Net IoT="none" NNm="FB1_12_Q" SNm="outreg<0>_MC.Q"/><Net IoT="none" NNm="FB1_11_Q" SNm="outreg<1>_MC.Q"/><Net IoT="none" NNm="FB1_10_Q" SNm="outreg<2>_MC.Q"/><Net IoT="none" NNm="FB2_16_Q" SNm="outreg<3>_MC.Q"/><Net IoT="none" NNm="FB2_15_Q" SNm="outreg<4>_MC.Q"/><Net IoT="none" NNm="FB1_10_I" SNm="column<0>_II/UIM"/><Net IoT="none" NNm="FB2_14_Q" SNm="outreg<5>_MC.Q"/><Net IoT="none" NNm="FB1_11_I" SNm="column<1>_II/UIM"/><Net IoT="none" NNm="FB1_12_I" SNm="column<2>_II/UIM"/><Net IoT="none" NNm="FB1_13_I" SNm="column<3>_II/UIM"/><Net IoT="none" NNm="FB1_1_OR" SNm="row<0>_MC.D"/><Net IoT="none" NNm="FB1_14_I" SNm="column<4>_II/UIM"/><Net IoT="none" NNm="FB1_2_OR" SNm="row<1>_MC.D"/><Net IoT="none" NNm="FB2_1_OR" SNm="out<1>_MC.Q"/><Net IoT="none" NNm="FB1_15_I" SNm="column<5>_II/UIM"/><Net IoT="none" NNm="FB1_3_OR" SNm="row<2>_MC.D"/><Net IoT="none" NNm="FB2_2_OR" SNm="out<2>_MC.Q"/><Net IoT="none" NNm="FB1_16_I" SNm="column<6>_II/UIM"/><Net IoT="none" NNm="FB1_4_OR" SNm="row<3>_MC.D"/><Net IoT="none" NNm="FB2_3_OR" SNm="out<3>_MC.Q"/><Net IoT="none" NNm="FB2_7_I" SNm="column<7>_II/UIM"/><Net IoT="none" NNm="FB1_5_OR" SNm="row<4>_MC.D"/><Net IoT="none" NNm="FB2_4_OR" SNm="out<4>_MC.Q"/><Net IoT="none" NNm="FB1_6_OR" SNm="row<5>_MC.D"/><Net IoT="none" NNm="FB1_7_OR" SNm="row<6>_MC.D"/><Net IoT="none" NNm="FB2_6_OR" SNm="out<5>_MC.Q"/><Net IoT="none" NNm="FB1_8_OR" SNm="row<7>_MC.D"/><Net IoT="none" NNm="FB1_9_OR" SNm="out<0>_MC.Q"/><Net IoT="none" NNm="FB1_1_Q" SNm="row<0>_MC.UIM"/><Net IoT="none" NNm="FB1_2_Q" SNm="row<1>_MC.UIM"/><Net IoT="none" NNm="FB1_1_MC_CLK" SNm="FB1_1_MC_CLK"/><Net IoT="none" NNm="FB1_3_Q" SNm="row<2>_MC.UIM"/><Net IoT="none" NNm="FB1_2_MC_CLK" SNm="FB1_2_MC_CLK"/><Net IoT="none" NNm="FB1_4_Q" SNm="row<3>_MC.UIM"/><Net IoT="none" NNm="FB1_3_MC_CLK" SNm="FB1_3_MC_CLK"/><Net IoT="none" NNm="FB1_5_Q" SNm="row<4>_MC.UIM"/><Net IoT="none" NNm="FB1_4_MC_CLK" SNm="FB1_4_MC_CLK"/><Net IoT="none" NNm="FB1_6_Q" SNm="row<5>_MC.UIM"/><Net IoT="none" NNm="FB1_5_MC_CLK" SNm="FB1_5_MC_CLK"/><Net IoT="none" NNm="FB1_7_Q" SNm="row<6>_MC.UIM"/><Net IoT="none" NNm="FB1_6_MC_CLK" SNm="FB1_6_MC_CLK"/><Net IoT="none" NNm="FB1_8_Q" SNm="row<7>_MC.UIM"/><Net IoT="none" NNm="FB1_7_MC_CLK" SNm="FB1_7_MC_CLK"/><Net IoT="none" NNm="FB1_8_MC_CLK" SNm="FB1_8_MC_CLK"/><Net IoT="none" NNm="FB1_10_OR" SNm="outreg<2>_MC.D"/><Net IoT="none" NNm="FB1_11_OR" SNm="outreg<1>_MC.D"/><Net IoT="none" NNm="FB2_5_I" SNm="clk_II/FCLK"/><Net IoT="none" NNm="FB1_12_OR" SNm="outreg<0>_MC.D"/><Net IoT="none" NNm="FB1_13_OR" SNm="_n010237"/><Net IoT="none" NNm="FB1_14_OR" SNm="_n009837"/><Net IoT="none" NNm="FB2_14_OR" SNm="outreg<5>_MC.D"/><Net IoT="none" NNm="FB2_15_OR" SNm="outreg<4>_MC.D"/><Net IoT="none" NNm="FB2_16_OR" SNm="outreg<3>_MC.D"/><Net IoT="none" NNm="FB1_10_MC_CLK" SNm="FB1_10_MC_CLK"/><Net IoT="none" NNm="FB1_11_MC_CLK" SNm="FB1_11_MC_CLK"/><Net IoT="none" NNm="FB1_12_MC_CLK" SNm="FB1_12_MC_CLK"/><Net IoT="none" NNm="FB2_14_MC_CLK" SNm="FB2_14_MC_CLK"/><Net IoT="none" NNm="FB2_15_MC_CLK" SNm="FB2_15_MC_CLK"/><Net IoT="none" NNm="FB2_16_MC_CLK" SNm="FB2_16_MC_CLK"/><Net IoT="none" NNm="PT_GND" SNm="PT_GND"/><Net IoT="none" NNm="FB1_PT0" SNm="FB1_PT0"/><Net IoT="none" NNm="FB1_PT1" SNm="FB1_PT1"/><Net IoT="none" NNm="FB2_PT0" SNm="FB2_PT0"/><Net IoT="none" NNm="FB1_PT2" SNm="FB1_PT2"/><Net IoT="none" NNm="FB2_PT1" SNm="FB2_PT1"/><Net IoT="none" NNm="FB1_PT3" SNm="FB1_PT3"/><Net IoT="none" NNm="FB2_PT2" SNm="FB2_PT2"/><Net IoT="none" NNm="FB1_PT4" SNm="FOOBAR1__ctinst/4"/><Net IoT="none" NNm="FB2_PT3" SNm="FB2_PT3"/><Net IoT="none" NNm="FB2_PT4" SNm="FOOBAR2__ctinst/4"/><Net IoT="none" NNm="FB1_PT5" SNm="FB1_PT5"/><Net IoT="none" NNm="FB1_PT6" SNm="FB1_PT6"/><Net IoT="none" NNm="FB2_PT5" SNm="FB2_PT5"/><Net IoT="none" NNm="FB1_PT7" SNm="FB1_PT7"/><Net IoT="none" NNm="FB2_PT6" SNm="FB2_PT6"/><Net IoT="none" NNm="FB1_PT8" SNm="FB1_PT8"/><Net IoT="none" NNm="FB2_PT7" SNm="FB2_PT7"/><Net IoT="none" NNm="FB1_PT9" SNm="FB1_PT9"/><Net IoT="none" NNm="FB2_PT8" SNm="FB2_PT8"/><Net IoT="none" NNm="FB2_PT9" SNm="FB2_PT9"/><Globals><GlblBuf Nm="GCK0" GType="GCK"><IPort NNm="FB2_5_I"/></GlblBuf></Globals><Lb Nm="FB1"><LbT Nm="FB1_PT0" PtT="XBR_CT_X"><OPort NNm="FB1_PT0"/><IPort NNm="FB1_8_Q"/></LbT><LbT Nm="FB1_PT1" PtT="XBR_CT_X"><OPort NNm="FB1_PT1"/><IPort NNm="FB1_1_Q"/></LbT><LbT Nm="FB1_PT2" PtT="XBR_CT_X"><OPort NNm="FB1_PT2"/><IPort NNm="FB1_2_Q"/></LbT><LbT Nm="FB1_PT3" PtT="XBR_CT_X"><OPort NNm="FB1_PT3"/><IPort NNm="FB1_3_Q"/></LbT><LbT Nm="FB1_PT4" PtT="XBR_CT"><OPort NNm="FB1_PT4"/><IPort NNm="FB1_PT55"/><IPort NNm="FB1_13_OR"/></LbT><LbT Nm="FB1_PT5" PtT="XBR_CT"><OPort NNm="FB1_PT5"/><IPort NNm="FB1_4_Q"/></LbT><LbT Nm="FB1_PT6" PtT="XBR_CT"><OPort NNm="FB1_PT6"/><IPort NNm="FB1_5_Q"/></LbT><LbT Nm="FB1_PT7" PtT="XBR_CT"><OPort NNm="FB1_PT7"/><IPort NNm="FB1_6_Q"/></LbT><LbT Nm="FB1_PT8" PtT="XBR_A"><OPort NNm="FB1_PT8"/><IPort NNm="FB1_7_Q"/></LbT><LbT Nm="FB1_PT9" PtT="XBR_B"><OPort NNm="FB1_PT9"/><IPort NNm="FB1_12_Q"/></LbT><LbT Nm="FB1_PT10" PtT="XBR_C"><OPort NNm="FB1_PT10"/><IPort NNm="FB2_7_I"/><IPort NNm="FB1_16_I"/><IPort NNm="FB1_15_I"/><IPort NNm="FB1_14_I"/><IPort NNm="FB1_13_I"/><IPort NNm="FB1_12_I"/><IPort NNm="FB1_11_I"/><IPort NNm="FB1_10_I"/></LbT><LbT Nm="FB1_PT11" PtT="XBR_A"><OPort NNm="FB1_PT11"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_2_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB1_4_Q"/><IPort NNm="FB1_5_Q"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB1_8_Q"/></LbT><LbT Nm="FB1_PT12" PtT="XBR_B"><OPort NNm="FB1_PT12"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_2_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB1_4_Q"/><IPort NNm="FB1_5_Q"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB1_8_Q"/></LbT><LbT Nm="FB1_PT13" PtT="XBR_C"><OPort NNm="FB1_PT13"/><IPort NNm="FB2_7_I"/><IPort NNm="FB1_16_I"/><IPort NNm="FB1_15_I"/><IPort NNm="FB1_14_I"/><IPort NNm="FB1_13_I"/><IPort NNm="FB1_12_I"/><IPort NNm="FB1_11_I"/><IPort NNm="FB1_10_I"/></LbT><LbT Nm="FB1_PT14" PtT="XBR_A"><OPort NNm="FB1_PT14"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_2_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB1_4_Q"/><IPort NNm="FB1_5_Q"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB1_8_Q"/></LbT><LbT Nm="FB1_PT15" PtT="XBR_B"><OPort NNm="FB1_PT15"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_2_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB1_4_Q"/><IPort NNm="FB1_5_Q"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB1_8_Q"/></LbT><LbT Nm="FB1_PT16" PtT="XBR_C"><OPort NNm="FB1_PT16"/><IPort NNm="FB2_7_I"/><IPort NNm="FB1_16_I"/><IPort NNm="FB1_15_I"/><IPort NNm="FB1_14_I"/><IPort NNm="FB1_13_I"/><IPort NNm="FB1_12_I"/><IPort NNm="FB1_11_I"/><IPort NNm="FB1_10_I"/></LbT><LbT Nm="FB1_PT17" PtT="XBR_A"><OPort NNm="FB1_PT17"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_2_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB1_4_Q"/><IPort NNm="FB1_5_Q"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB1_8_Q"/></LbT><LbT Nm="FB1_PT18" PtT="XBR_B"><OPort NNm="FB1_PT18"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_2_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB1_4_Q"/><IPort NNm="FB1_5_Q"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB1_8_Q"/></LbT><LbT Nm="FB1_PT19" PtT="XBR_C"><OPort NNm="FB1_PT19"/><IPort NNm="FB2_7_I"/><IPort NNm="FB1_16_I"/><IPort NNm="FB1_15_I"/><IPort NNm="FB1_14_I"/><IPort NNm="FB1_13_I"/><IPort NNm="FB1_12_I"/><IPort NNm="FB1_11_I"/><IPort NNm="FB1_10_I"/></LbT><LbT Nm="FB1_PT20" PtT="XBR_A"><OPort NNm="FB1_PT20"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_2_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB1_4_Q"/><IPort NNm="FB1_5_Q"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB1_8_Q"/></LbT><LbT Nm="FB1_PT21" PtT="XBR_B"><OPort NNm="FB1_PT21"/><IPort NNm="FB2_7_I"/><IPort NNm="FB1_16_I"/><IPort NNm="FB1_15_I"/><IPort NNm="FB1_14_I"/><IPort NNm="FB1_13_I"/><IPort NNm="FB1_12_I"/><IPort NNm="FB1_11_I"/><IPort NNm="FB1_10_I"/></LbT><LbT Nm="FB1_PT22" PtT="XBR_C"><OPort NNm="FB1_PT22"/><IPort NNm="FB2_7_I"/><IPort NNm="FB1_16_I"/><IPort NNm="FB1_15_I"/><IPort NNm="FB1_14_I"/><IPort NNm="FB1_13_I"/><IPort NNm="FB1_12_I"/><IPort NNm="FB1_11_I"/><IPort NNm="FB1_10_I"/></LbT><LbT Nm="FB1_PT23" PtT="XBR_A"><OPort NNm="FB1_PT23"/><IPort NNm="FB2_7_I"/><IPort NNm="FB1_16_I"/><IPort NNm="FB1_15_I"/><IPort NNm="FB1_14_I"/><IPort NNm="FB1_13_I"/><IPort NNm="FB1_12_I"/><IPort NNm="FB1_11_I"/><IPort NNm="FB1_10_I"/></LbT><LbT Nm="FB1_PT24" PtT="XBR_B"><OPort NNm="FB1_PT24"/><IPort NNm="FB2_7_I"/><IPort NNm="FB1_16_I"/><IPort NNm="FB1_15_I"/><IPort NNm="FB1_14_I"/><IPort NNm="FB1_13_I"/><IPort NNm="FB1_12_I"/><IPort NNm="FB1_11_I"/><IPort NNm="FB1_10_I"/></LbT><LbT Nm="FB1_PT25" PtT="XBR_C"><OPort NNm="FB1_PT25"/><IPort NNm="FB2_7_I"/><IPort NNm="FB1_16_I"/><IPort NNm="FB1_15_I"/><IPort NNm="FB1_14_I"/><IPort NNm="FB1_13_I"/><IPort NNm="FB1_12_I"/><IPort NNm="FB1_11_I"/><IPort NNm="FB1_10_I"/></LbT><LbT Nm="FB1_PT26" PtT="XBR_A"><OPort NNm="FB1_PT26"/><IPort NNm="FB2_7_I"/><IPort NNm="FB1_16_I"/><IPort NNm="FB1_15_I"/><IPort NNm="FB1_14_I"/><IPort NNm="FB1_13_I"/><IPort NNm="FB1_12_I"/><IPort NNm="FB1_11_I"/><IPort NNm="FB1_10_I"/></LbT><LbT Nm="FB1_PT27" PtT="XBR_B"><OPort NNm="FB1_PT27"/><IPort NNm="FB2_7_I"/><IPort NNm="FB1_16_I"/><IPort NNm="FB1_15_I"/><IPort NNm="FB1_14_I"/><IPort NNm="FB1_13_I"/><IPort NNm="FB1_12_I"/><IPort NNm="FB1_11_I"/><IPort NNm="FB1_10_I"/></LbT><LbT Nm="FB1_PT28" PtT="XBR_C"><OPort NNm="FB1_PT28"/><IPort NNm="FB2_7_I"/><IPort NNm="FB1_16_I"/><IPort NNm="FB1_15_I"/><IPort NNm="FB1_14_I"/><IPort NNm="FB1_13_I"/><IPort NNm="FB1_12_I"/><IPort NNm="FB1_11_I"/><IPort NNm="FB1_10_I"/></LbT><LbT Nm="FB1_PT29" PtT="XBR_A"><OPort NNm="FB1_PT29"/><IPort NNm="FB2_7_I"/><IPort NNm="FB1_16_I"/><IPort NNm="FB1_15_I"/><IPort NNm="FB1_14_I"/><IPort NNm="FB1_13_I"/><IPort NNm="FB1_12_I"/><IPort NNm="FB1_11_I"/><IPort NNm="FB1_10_I"/></LbT><LbT Nm="FB1_PT30" PtT="XBR_B"><OPort NNm="FB1_PT30"/><IPort NNm="FB2_7_I"/><IPort NNm="FB1_16_I"/><IPort NNm="FB1_15_I"/><IPort NNm="FB1_14_I"/><IPort NNm="FB1_13_I"/><IPort NNm="FB1_12_I"/><IPort NNm="FB1_11_I"/><IPort NNm="FB1_10_I"/></LbT><LbT Nm="FB1_PT31" PtT="XBR_C"><OPort NNm="FB1_PT31"/><IPort NNm="FB2_7_I"/><IPort NNm="FB1_16_I"/><IPort NNm="FB1_15_I"/><IPort NNm="FB1_14_I"/><IPort NNm="FB1_13_I"/><IPort NNm="FB1_12_I"/><IPort NNm="FB1_11_I"/><IPort NNm="FB1_10_I"/></LbT><LbT Nm="FB1_PT32" PtT="XBR_A"><OPort NNm="FB1_PT32"/><IPort NNm="FB1_PT55"/></LbT><LbT Nm="FB1_PT52" PtT="XBR_C"><OPort NNm="FB1_PT52"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_2_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB1_4_Q"/><IPort NNm="FB1_5_Q"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB1_8_Q"/></LbT><LbT Nm="FB1_PT55" PtT="XBR_C"><OPort NNm="FB1_PT55"/><IPort NNm="FB2_7_I"/><IPort NNm="FB1_16_I"/><IPort NNm="FB1_15_I"/><IPort NNm="FB1_14_I"/><IPort NNm="FB1_13_I"/><IPort NNm="FB1_12_I"/><IPort NNm="FB1_11_I"/><IPort NNm="FB1_10_I"/></LbT><Mc Nm="FB1_1"><ClkMux Nm="FB1_1_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_1_MC_CLK"/></ClkMux><FbMux Nm="FB1_1_N"><IPort NNm="FB1_1_Q"/></FbMux><InBuf Nm="FB1_1_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="row<0>"/></InBuf><OutBuf Nm="FB1_1_O" IOS="LVCMOS18"><IPort NNm="FB1_1_Q"/><OPort NNm="row<0>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_1_FF"><FlopPort NNm="FB1_1_OR" Port="D"/><FlopPort NNm="FB1_1_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_1_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB1_PT10" Port="CE"/></DFlop><Or Nm="FB1_1_OR"><OPort NNm="FB1_1_OR"/><IPort NNm="FB1_PT0"/></Or></Mc><Mc Nm="FB1_2"><ClkMux Nm="FB1_2_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_2_MC_CLK"/></ClkMux><FbMux Nm="FB1_2_N"><IPort NNm="FB1_2_Q"/></FbMux><InBuf Nm="FB1_2_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="row<1>"/></InBuf><OutBuf Nm="FB1_2_O" IOS="LVCMOS18"><IPort NNm="FB1_2_Q"/><OPort NNm="row<1>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_2_FF"><FlopPort NNm="FB1_2_OR" Port="D"/><FlopPort NNm="FB1_2_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_2_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB1_PT10" Port="CE"/></DFlop><Or Nm="FB1_2_OR"><OPort NNm="FB1_2_OR"/><IPort NNm="FB1_PT1"/></Or></Mc><Mc Nm="FB1_3"><ClkMux Nm="FB1_3_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_3_MC_CLK"/></ClkMux><FbMux Nm="FB1_3_N"><IPort NNm="FB1_3_Q"/></FbMux><InBuf Nm="FB1_3_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="row<2>"/></InBuf><OutBuf Nm="FB1_3_O" IOS="LVCMOS18"><IPort NNm="FB1_3_Q"/><OPort NNm="row<2>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_3_FF"><FlopPort NNm="FB1_3_OR" Port="D"/><FlopPort NNm="FB1_3_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_3_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB1_PT10" Port="CE"/></DFlop><Or Nm="FB1_3_OR"><OPort NNm="FB1_3_OR"/><IPort NNm="FB1_PT2"/></Or></Mc><Mc Nm="FB1_4"><ClkMux Nm="FB1_4_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_4_MC_CLK"/></ClkMux><FbMux Nm="FB1_4_N"><IPort NNm="FB1_4_Q"/></FbMux><InBuf Nm="FB1_4_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="row<3>"/></InBuf><OutBuf Nm="FB1_4_O" IOS="LVCMOS18"><IPort NNm="FB1_4_Q"/><OPort NNm="row<3>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_4_FF"><FlopPort NNm="FB1_4_OR" Port="D"/><FlopPort NNm="FB1_4_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_4_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB1_PT10" Port="CE"/></DFlop><Or Nm="FB1_4_OR"><OPort NNm="FB1_4_OR"/><IPort NNm="FB1_PT3"/></Or></Mc><Mc Nm="FB1_5"><ClkMux Nm="FB1_5_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_5_MC_CLK"/></ClkMux><FbMux Nm="FB1_5_N"><IPort NNm="FB1_5_Q"/></FbMux><InBuf Nm="FB1_5_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="row<4>"/></InBuf><OutBuf Nm="FB1_5_O" IOS="LVCMOS18"><IPort NNm="FB1_5_Q"/><OPort NNm="row<4>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_5_FF"><FlopPort NNm="FB1_5_OR" Port="D"/><FlopPort NNm="FB1_5_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_5_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB1_PT10" Port="CE"/></DFlop><Or Nm="FB1_5_OR"><OPort NNm="FB1_5_OR"/><IPort NNm="FB1_PT5"/></Or></Mc><Mc Nm="FB1_6"><ClkMux Nm="FB1_6_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_6_MC_CLK"/></ClkMux><FbMux Nm="FB1_6_N"><IPort NNm="FB1_6_Q"/></FbMux><InBuf Nm="FB1_6_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="row<5>"/></InBuf><OutBuf Nm="FB1_6_O" IOS="LVCMOS18"><IPort NNm="FB1_6_Q"/><OPort NNm="row<5>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_6_FF"><FlopPort NNm="FB1_6_OR" Port="D"/><FlopPort NNm="FB1_6_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_6_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB1_PT10" Port="CE"/></DFlop><Or Nm="FB1_6_OR"><OPort NNm="FB1_6_OR"/><IPort NNm="FB1_PT6"/></Or></Mc><Mc Nm="FB1_7"><ClkMux Nm="FB1_7_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_7_MC_CLK"/></ClkMux><FbMux Nm="FB1_7_N"><IPort NNm="FB1_7_Q"/></FbMux><InBuf Nm="FB1_7_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="row<6>"/></InBuf><OutBuf Nm="FB1_7_O" IOS="LVCMOS18"><IPort NNm="FB1_7_Q"/><OPort NNm="row<6>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_7_FF"><FlopPort NNm="FB1_7_OR" Port="D"/><FlopPort NNm="FB1_7_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_7_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB1_PT10" Port="CE"/></DFlop><Or Nm="FB1_7_OR"><OPort NNm="FB1_7_OR"/><IPort NNm="FB1_PT7"/></Or></Mc><Mc Nm="FB1_8"><ClkMux Nm="FB1_8_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_8_MC_CLK"/></ClkMux><FbMux Nm="FB1_8_N"><IPort NNm="FB1_8_Q"/></FbMux><InBuf Nm="FB1_8_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="row<7>"/></InBuf><OutBuf Nm="FB1_8_O" IOS="LVCMOS18"><IPort NNm="FB1_8_Q"/><OPort NNm="row<7>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_8_FF"><FlopPort NNm="FB1_8_OR" Port="D"/><FlopPort NNm="FB1_8_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_8_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB1_PT10" Port="CE"/></DFlop><Or Nm="FB1_8_OR"><OPort NNm="FB1_8_OR"/><IPort NNm="FB1_PT8"/></Or></Mc><Mc Nm="FB1_9"><InBuf Nm="FB1_9_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="out<0>"/></InBuf><OutBuf Nm="FB1_9_O" IOS="LVCMOS18"><IPort NNm="FB1_9_OR"/><OPort NNm="out<0>"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB1_9_OR"><OPort NNm="FB1_9_OR"/><IPort NNm="FB1_PT9"/><IPort NNm="FB1_PT10"/></Or></Mc><Mc Nm="FB1_10"><ClkMux Nm="FB1_10_MC_CLK" Rate="1"><IPort NNm="FB1_PT4"/><OPort NNm="FB1_10_MC_CLK"/></ClkMux><FbMux Nm="FB1_10_N"><IPort NNm="FB1_10_Q"/></FbMux><FbMux Nm="FB1_10_P"><IPort NNm="FB1_10_I"/></FbMux><InBuf Nm="FB1_10_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="column<0>"/><OPort NNm="FB1_10_I"/></InBuf><DFlop Nm="FB1_10_FF"><FlopPort NNm="FB1_10_OR" Port="D"/><FlopPort NNm="FB1_10_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_10_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB1_10_OR"><OPort NNm="FB1_10_OR"/><IPort NNm="FB1_PT32"/><IPort NNm="FB1_PT24"/><IPort NNm="FB1_PT23"/><IPort NNm="FB1_PT21"/></Or></Mc><Mc Nm="FB1_11"><ClkMux Nm="FB1_11_MC_CLK" Rate="1"><IPort NNm="FB1_PT4"/><OPort NNm="FB1_11_MC_CLK"/></ClkMux><FbMux Nm="FB1_11_N"><IPort NNm="FB1_11_Q"/></FbMux><FbMux Nm="FB1_11_P"><IPort NNm="FB1_11_I"/></FbMux><InBuf Nm="FB1_11_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="column<1>"/><OPort NNm="FB1_11_I"/></InBuf><DFlop Nm="FB1_11_FF"><FlopPort NNm="FB1_11_OR" Port="D"/><FlopPort NNm="FB1_11_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_11_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB1_11_OR"><OPort NNm="FB1_11_OR"/><IPort NNm="FB1_PT32"/><IPort NNm="FB1_PT27"/><IPort NNm="FB1_PT26"/><IPort NNm="FB1_PT21"/></Or></Mc><Mc Nm="FB1_12"><ClkMux Nm="FB1_12_MC_CLK" Rate="1"><IPort NNm="FB1_PT4"/><OPort NNm="FB1_12_MC_CLK"/></ClkMux><FbMux Nm="FB1_12_N"><IPort NNm="FB1_12_Q"/></FbMux><FbMux Nm="FB1_12_P"><IPort NNm="FB1_12_I"/></FbMux><InBuf Nm="FB1_12_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="column<2>"/><OPort NNm="FB1_12_I"/></InBuf><DFlop Nm="FB1_12_FF"><FlopPort NNm="FB1_12_OR" Port="D"/><FlopPort NNm="FB1_12_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_12_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB1_12_OR"><OPort NNm="FB1_12_OR"/><IPort NNm="FB1_PT29"/><IPort NNm="FB1_PT26"/><IPort NNm="FB1_PT23"/><IPort NNm="FB1_PT21"/></Or></Mc><Mc Nm="FB1_13"><FbMux Nm="FB1_13_N"><IPort NNm="FB1_13_OR"/></FbMux><FbMux Nm="FB1_13_P"><IPort NNm="FB1_13_I"/></FbMux><InBuf Nm="FB1_13_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="column<3>"/><OPort NNm="FB1_13_I"/></InBuf><Or Nm="FB1_13_OR"><OPort NNm="FB1_13_OR"/><IPort NNm="FB1_PT30"/><IPort NNm="FB1_PT29"/><IPort NNm="FB1_PT27"/><IPort NNm="FB1_PT26"/><IPort NNm="FB1_PT24"/><IPort NNm="FB1_PT23"/><IPort NNm="FB1_PT21"/></Or></Mc><Mc Nm="FB1_14"><FbMux Nm="FB1_14_N"><IPort NNm="FB1_14_OR"/></FbMux><FbMux Nm="FB1_14_P"><IPort NNm="FB1_14_I"/></FbMux><InBuf Nm="FB1_14_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="column<4>"/><OPort NNm="FB1_14_I"/></InBuf><Or Nm="FB1_14_OR"><OPort NNm="FB1_14_OR"/><IPort NNm="FB1_PT17"/><IPort NNm="FB1_PT12"/><IPort NNm="FB1_PT20"/><IPort NNm="FB1_PT15"/><IPort NNm="FB1_PT14"/><IPort NNm="FB1_PT18"/><IPort NNm="FB1_PT11"/></Or></Mc><Mc Nm="FB1_15"><XorMux Nm="FB1_15_AND"><IPort NNm="FB1_PT52"/></XorMux><FbMux Nm="FB1_15_N"><IPort NNm="FB1_PT52"/></FbMux><FbMux Nm="FB1_15_P"><IPort NNm="FB1_15_I"/></FbMux><InBuf Nm="FB1_15_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="column<5>"/><OPort NNm="FB1_15_I"/></InBuf></Mc><Mc Nm="FB1_16"><XorMux Nm="FB1_16_AND"><IPort NNm="FB1_PT55"/></XorMux><FbMux Nm="FB1_16_N"><IPort NNm="FB1_PT55"/></FbMux><FbMux Nm="FB1_16_P"><IPort NNm="FB1_16_I"/></FbMux><InBuf Nm="FB1_16_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="column<6>"/><OPort NNm="FB1_16_I"/></InBuf></Mc></Lb><Lb Nm="FB2"><LbT Nm="FB2_PT0" PtT="XBR_CT_X"><OPort NNm="FB2_PT0"/><IPort NNm="FB2_7_I"/><IPort NNm="FB1_16_I"/><IPort NNm="FB1_15_I"/><IPort NNm="FB1_14_I"/><IPort NNm="FB1_13_I"/><IPort NNm="FB1_12_I"/><IPort NNm="FB1_11_I"/><IPort NNm="FB1_10_I"/></LbT><LbT Nm="FB2_PT1" PtT="XBR_CT_X"><OPort NNm="FB2_PT1"/><IPort NNm="FB1_11_Q"/></LbT><LbT Nm="FB2_PT2" PtT="XBR_CT_X"><OPort NNm="FB2_PT2"/><IPort NNm="FB1_10_Q"/></LbT><LbT Nm="FB2_PT3" PtT="XBR_CT_X"><OPort NNm="FB2_PT3"/><IPort NNm="FB2_16_Q"/></LbT><LbT Nm="FB2_PT4" PtT="XBR_CT"><OPort NNm="FB2_PT4"/><IPort NNm="FB1_14_OR"/><IPort NNm="FB1_PT52"/></LbT><LbT Nm="FB2_PT5" PtT="XBR_CT"><OPort NNm="FB2_PT5"/><IPort NNm="FB2_15_Q"/></LbT><LbT Nm="FB2_PT6" PtT="XBR_CT"><OPort NNm="FB2_PT6"/><IPort NNm="FB2_14_Q"/></LbT><LbT Nm="FB2_PT7" PtT="XBR_CT"><OPort NNm="FB2_PT7"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_2_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB1_4_Q"/><IPort NNm="FB1_5_Q"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB1_8_Q"/></LbT><LbT Nm="FB2_PT8" PtT="XBR_A"><OPort NNm="FB2_PT8"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_2_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB1_4_Q"/><IPort NNm="FB1_5_Q"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB1_8_Q"/></LbT><LbT Nm="FB2_PT9" PtT="XBR_B"><OPort NNm="FB2_PT9"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_2_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB1_4_Q"/><IPort NNm="FB1_5_Q"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB1_8_Q"/></LbT><LbT Nm="FB2_PT10" PtT="XBR_C"><OPort NNm="FB2_PT10"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_2_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB1_4_Q"/><IPort NNm="FB1_5_Q"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB1_8_Q"/></LbT><LbT Nm="FB2_PT11" PtT="XBR_A"><OPort NNm="FB2_PT11"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_2_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB1_4_Q"/><IPort NNm="FB1_5_Q"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB1_8_Q"/></LbT><LbT Nm="FB2_PT12" PtT="XBR_B"><OPort NNm="FB2_PT12"/><IPort NNm="FB1_PT52"/></LbT><LbT Nm="FB2_PT13" PtT="XBR_C"><OPort NNm="FB2_PT13"/><IPort NNm="FB1_1_Q"/><IPort NNm="FB1_2_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB1_4_Q"/><IPort NNm="FB1_5_Q"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB1_8_Q"/></LbT><Mc Nm="FB2_1"><InBuf Nm="FB2_1_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="out<1>"/></InBuf><OutBuf Nm="FB2_1_O" IOS="LVCMOS18"><IPort NNm="FB2_1_OR"/><OPort NNm="out<1>"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB2_1_OR"><OPort NNm="FB2_1_OR"/><IPort NNm="FB2_PT1"/><IPort NNm="FB2_PT0"/></Or></Mc><Mc Nm="FB2_2"><InBuf Nm="FB2_2_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="out<2>"/></InBuf><OutBuf Nm="FB2_2_O" IOS="LVCMOS18"><IPort NNm="FB2_2_OR"/><OPort NNm="out<2>"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB2_2_OR"><OPort NNm="FB2_2_OR"/><IPort NNm="FB2_PT2"/><IPort NNm="FB2_PT0"/></Or></Mc><Mc Nm="FB2_3"><InBuf Nm="FB2_3_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="out<3>"/></InBuf><OutBuf Nm="FB2_3_O" IOS="LVCMOS18"><IPort NNm="FB2_3_OR"/><OPort NNm="out<3>"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB2_3_OR"><OPort NNm="FB2_3_OR"/><IPort NNm="FB2_PT3"/><IPort NNm="FB2_PT0"/></Or></Mc><Mc Nm="FB2_4"><InBuf Nm="FB2_4_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="out<4>"/></InBuf><OutBuf Nm="FB2_4_O" IOS="LVCMOS18"><IPort NNm="FB2_4_OR"/><OPort NNm="out<4>"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB2_4_OR"><OPort NNm="FB2_4_OR"/><IPort NNm="FB2_PT5"/><IPort NNm="FB2_PT0"/></Or></Mc><Mc Nm="FB2_5"><InBuf Nm="FB2_5_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="clk"/><OPort NNm="FB2_5_I"/></InBuf></Mc><Mc Nm="FB2_6"><InBuf Nm="FB2_6_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="out<5>"/></InBuf><OutBuf Nm="FB2_6_O" IOS="LVCMOS18"><IPort NNm="FB2_6_OR"/><OPort NNm="out<5>"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB2_6_OR"><OPort NNm="FB2_6_OR"/><IPort NNm="FB2_PT6"/><IPort NNm="FB2_PT0"/></Or></Mc><Mc Nm="FB2_7"><FbMux Nm="FB2_7_P"><IPort NNm="FB2_7_I"/></FbMux><InBuf Nm="FB2_7_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="column<7>"/><OPort NNm="FB2_7_I"/></InBuf></Mc><Mc Nm="FB2_8"/><Mc Nm="FB2_9"/><Mc Nm="FB2_10"/><Mc Nm="FB2_11"/><Mc Nm="FB2_12"/><Mc Nm="FB2_13"/><Mc Nm="FB2_14"><ClkMux Nm="FB2_14_MC_CLK" Rate="1"><IPort NNm="FB2_PT4"/><OPort NNm="FB2_14_MC_CLK"/></ClkMux><FbMux Nm="FB2_14_N"><IPort NNm="FB2_14_Q"/></FbMux><DFlop Nm="FB2_14_FF"><FlopPort NNm="FB2_14_OR" Port="D"/><FlopPort NNm="FB2_14_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_14_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB2_14_OR"><OPort NNm="FB2_14_OR"/><IPort NNm="FB2_PT12"/><IPort NNm="FB2_PT10"/><IPort NNm="FB2_PT7"/><IPort NNm="FB2_PT13"/></Or></Mc><Mc Nm="FB2_15"><ClkMux Nm="FB2_15_MC_CLK" Rate="1"><IPort NNm="FB2_PT4"/><OPort NNm="FB2_15_MC_CLK"/></ClkMux><FbMux Nm="FB2_15_N"><IPort NNm="FB2_15_Q"/></FbMux><DFlop Nm="FB2_15_FF"><FlopPort NNm="FB2_15_OR" Port="D"/><FlopPort NNm="FB2_15_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_15_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB2_15_OR"><OPort NNm="FB2_15_OR"/><IPort NNm="FB2_PT12"/><IPort NNm="FB2_PT10"/><IPort NNm="FB2_PT9"/><IPort NNm="FB2_PT11"/></Or></Mc><Mc Nm="FB2_16"><ClkMux Nm="FB2_16_MC_CLK" Rate="1"><IPort NNm="FB2_PT4"/><OPort NNm="FB2_16_MC_CLK"/></ClkMux><FbMux Nm="FB2_16_N"><IPort NNm="FB2_16_Q"/></FbMux><DFlop Nm="FB2_16_FF"><FlopPort NNm="FB2_16_OR" Port="D"/><FlopPort NNm="FB2_16_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_16_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB2_16_OR"><OPort NNm="FB2_16_OR"/><IPort NNm="FB2_PT8"/><IPort NNm="FB2_PT10"/><IPort NNm="FB2_PT7"/><IPort NNm="FB2_PT9"/></Or></Mc></Lb></Document>
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