keypadscan_timesim.v

适用于FPGA的SOPC方面的元器件添加

// Xilinx Verilog netlist produced by netgen application (version G.38)
// Command      : -w -ofmt verilog -sim KeypadScan.nga KeypadScan_timesim.v 
// Input file   : KeypadScan.nga
// Output file  : KeypadScan_timesim.v
// Design name  : KeypadScan.nga
// # of Modules : 1
// Xilinx       : C:/Xilinx63
// Device       : XC2C32A-6-CP56 (Speed File: Version 9.0 Advance Product Specification)

// This verilog netlist is a simulation model and uses simulation 
// primitives which may not represent the true implementation of the 
// device, however the netlist is functionally correct and should not 
// be modified. This file cannot be synthesized and should only be used 
// with supported simulation tools.

`timescale 1 ns/1 ps

module KeypadScan (
  clk, column, out, row
);
  input clk;
  input [7 : 0] column;
  output [5 : 0] out;
  output [7 : 0] row;
  wire \clk_II/FCLK ;
  wire \column<0>_II/UIM ;
  wire \column<1>_II/UIM ;
  wire \column<2>_II/UIM ;
  wire \column<3>_II/UIM ;
  wire \column<4>_II/UIM ;
  wire \column<5>_II/UIM ;
  wire \column<6>_II/UIM ;
  wire \column<7>_II/UIM ;
  wire \out<0>_MC.Q ;
  wire \out<1>_MC.Q ;
  wire \out<2>_MC.Q ;
  wire \out<3>_MC.Q ;
  wire \out<4>_MC.Q ;
  wire \out<5>_MC.Q ;
  wire \row<0>_MC.Q ;
  wire \row<1>_MC.Q ;
  wire \row<2>_MC.Q ;
  wire \row<3>_MC.Q ;
  wire \row<4>_MC.Q ;
  wire \row<5>_MC.Q ;
  wire \row<6>_MC.Q ;
  wire \row<7>_MC.Q ;
  wire \out<0>_MC.Q_tsimrenamed_net_ ;
  wire \out<0>_MC.D ;
  wire \out<0>_MC.D1 ;
  wire \out<0>_MC.D2 ;
  wire \out<0>_MC.D2_PT_0 ;
  wire \out<0>_MC.D2_PT_1 ;
  wire \outreg<0>_MC.Q ;
  wire \outreg<0>_MC.D ;
  wire \FOOBAR1__ctinst/4 ;
  wire \outreg<0>_MC.REG_tsimcreated_inv_FOOBAR1__ctinst/4 ;
  wire Gnd;
  wire PRLD = glbl.PRLD;
  wire Vcc;
  wire \outreg<0>_MC.D1 ;
  wire \outreg<0>_MC.D2 ;
  wire \outreg<0>_MC.D2_PT_0 ;
  wire \outreg<0>_MC.D2_PT_1 ;
  wire \outreg<0>_MC.D2_PT_2 ;
  wire \outreg<0>_MC.D2_PT_3 ;
  wire \_n010237_MC.Q ;
  wire _n010237;
  wire \_n010237_MC.D ;
  wire \_n010237_MC.D1 ;
  wire \_n010237_MC.D2 ;
  wire \_n010237_MC.D2_PT_0 ;
  wire \_n010237_MC.D2_PT_1 ;
  wire \_n010237_MC.D2_PT_2 ;
  wire \_n010237_MC.D2_PT_3 ;
  wire \_n010237_MC.D2_PT_4 ;
  wire \_n010237_MC.D2_PT_5 ;
  wire \_n010237_MC.D2_PT_6 ;
  wire \N_PZ_96_MC.Q ;
  wire N_PZ_96;
  wire \N_PZ_96_MC.D ;
  wire \N_PZ_96_MC.D1 ;
  wire \N_PZ_96_MC.D2 ;
  wire \out<1>_MC.Q_tsimrenamed_net_ ;
  wire \out<1>_MC.D ;
  wire \out<1>_MC.D1 ;
  wire \out<1>_MC.D2 ;
  wire \out<1>_MC.D2_PT_0 ;
  wire \out<1>_MC.D2_PT_1 ;
  wire \outreg<1>_MC.Q ;
  wire \outreg<1>_MC.D ;
  wire \outreg<1>_MC.REG_tsimcreated_inv_FOOBAR1__ctinst/4 ;
  wire \outreg<1>_MC.D1 ;
  wire \outreg<1>_MC.D2 ;
  wire \outreg<1>_MC.D2_PT_0 ;
  wire \outreg<1>_MC.D2_PT_1 ;
  wire \outreg<1>_MC.D2_PT_2 ;
  wire \outreg<1>_MC.D2_PT_3 ;
  wire \out<2>_MC.Q_tsimrenamed_net_ ;
  wire \out<2>_MC.D ;
  wire \out<2>_MC.D1 ;
  wire \out<2>_MC.D2 ;
  wire \out<2>_MC.D2_PT_0 ;
  wire \out<2>_MC.D2_PT_1 ;
  wire \outreg<2>_MC.Q ;
  wire \outreg<2>_MC.D ;
  wire \outreg<2>_MC.REG_tsimcreated_inv_FOOBAR1__ctinst/4 ;
  wire \outreg<2>_MC.D1 ;
  wire \outreg<2>_MC.D2 ;
  wire \outreg<2>_MC.D2_PT_0 ;
  wire \outreg<2>_MC.D2_PT_1 ;
  wire \outreg<2>_MC.D2_PT_2 ;
  wire \outreg<2>_MC.D2_PT_3 ;
  wire \out<3>_MC.Q_tsimrenamed_net_ ;
  wire \out<3>_MC.D ;
  wire \out<3>_MC.D1 ;
  wire \out<3>_MC.D2 ;
  wire \out<3>_MC.D2_PT_0 ;
  wire \out<3>_MC.D2_PT_1 ;
  wire \outreg<3>_MC.Q ;
  wire \outreg<3>_MC.D ;
  wire \FOOBAR2__ctinst/4 ;
  wire \outreg<3>_MC.REG_tsimcreated_inv_FOOBAR2__ctinst/4 ;
  wire \outreg<3>_MC.D1 ;
  wire \outreg<3>_MC.D2 ;
  wire \row<2>_MC.UIM ;
  wire \row<3>_MC.UIM ;
  wire \row<4>_MC.UIM ;
  wire \row<5>_MC.UIM ;
  wire \row<6>_MC.UIM ;
  wire \row<7>_MC.UIM ;
  wire \row<0>_MC.UIM ;
  wire \row<1>_MC.UIM ;
  wire \outreg<3>_MC.D2_PT_0 ;
  wire \outreg<3>_MC.D2_PT_1 ;
  wire \outreg<3>_MC.D2_PT_2 ;
  wire \outreg<3>_MC.D2_PT_3 ;
  wire \row<2>_MC.Q_tsimrenamed_net_ ;
  wire \row<2>_MC.D ;
  wire \row<2>_MC.CE ;
  wire \row<2>_MC.D1 ;
  wire \row<2>_MC.D2 ;
  wire \row<1>_MC.Q_tsimrenamed_net_ ;
  wire \row<1>_MC.D ;
  wire \row<1>_MC.CE ;
  wire \row<1>_MC.D1 ;
  wire \row<1>_MC.D2 ;
  wire \row<0>_MC.Q_tsimrenamed_net_ ;
  wire \row<0>_MC.D ;
  wire \row<0>_MC.CE ;
  wire \row<0>_MC.D1 ;
  wire \row<0>_MC.D2 ;
  wire \row<7>_MC.Q_tsimrenamed_net_ ;
  wire \row<7>_MC.D ;
  wire \row<7>_MC.CE ;
  wire \row<7>_MC.D1 ;
  wire \row<7>_MC.D2 ;
  wire \row<6>_MC.Q_tsimrenamed_net_ ;
  wire \row<6>_MC.D ;
  wire \row<6>_MC.CE ;
  wire \row<6>_MC.D1 ;
  wire \row<6>_MC.D2 ;
  wire \row<5>_MC.Q_tsimrenamed_net_ ;
  wire \row<5>_MC.D ;
  wire \row<5>_MC.CE ;
  wire \row<5>_MC.D1 ;
  wire \row<5>_MC.D2 ;
  wire \row<4>_MC.Q_tsimrenamed_net_ ;
  wire \row<4>_MC.D ;
  wire \row<4>_MC.CE ;
  wire \row<4>_MC.D1 ;
  wire \row<4>_MC.D2 ;
  wire \row<3>_MC.Q_tsimrenamed_net_ ;
  wire \row<3>_MC.D ;
  wire \row<3>_MC.CE ;
  wire \row<3>_MC.D1 ;
  wire \row<3>_MC.D2 ;
  wire \_n009837_MC.Q ;
  wire _n009837;
  wire \_n009837_MC.D ;
  wire \_n009837_MC.D1 ;
  wire \_n009837_MC.D2 ;
  wire \_n009837_MC.D2_PT_0 ;
  wire \_n009837_MC.D2_PT_1 ;
  wire \_n009837_MC.D2_PT_2 ;
  wire \_n009837_MC.D2_PT_3 ;
  wire \_n009837_MC.D2_PT_4 ;
  wire \_n009837_MC.D2_PT_5 ;
  wire \_n009837_MC.D2_PT_6 ;
  wire \N_PZ_98_MC.Q ;
  wire N_PZ_98;
  wire \N_PZ_98_MC.D ;
  wire \N_PZ_98_MC.D1 ;
  wire \N_PZ_98_MC.D2 ;
  wire \out<4>_MC.Q_tsimrenamed_net_ ;
  wire \out<4>_MC.D ;
  wire \out<4>_MC.D1 ;
  wire \out<4>_MC.D2 ;
  wire \out<4>_MC.D2_PT_0 ;
  wire \out<4>_MC.D2_PT_1 ;
  wire \outreg<4>_MC.Q ;
  wire \outreg<4>_MC.D ;
  wire \outreg<4>_MC.REG_tsimcreated_inv_FOOBAR2__ctinst/4 ;
  wire \outreg<4>_MC.D1 ;
  wire \outreg<4>_MC.D2 ;
  wire \outreg<4>_MC.D2_PT_0 ;
  wire \outreg<4>_MC.D2_PT_1 ;
  wire \outreg<4>_MC.D2_PT_2 ;
  wire \outreg<4>_MC.D2_PT_3 ;
  wire \out<5>_MC.Q_tsimrenamed_net_ ;
  wire \out<5>_MC.D ;
  wire \out<5>_MC.D1 ;
  wire \out<5>_MC.D2 ;
  wire \out<5>_MC.D2_PT_0 ;
  wire \out<5>_MC.D2_PT_1 ;
  wire \outreg<5>_MC.Q ;
  wire \outreg<5>_MC.D ;
  wire \outreg<5>_MC.REG_tsimcreated_inv_FOOBAR2__ctinst/4 ;
  wire \outreg<5>_MC.D1 ;
  wire \outreg<5>_MC.D2 ;
  wire \outreg<5>_MC.D2_PT_0 ;
  wire \outreg<5>_MC.D2_PT_1 ;
  wire \outreg<5>_MC.D2_PT_2 ;
  wire \outreg<5>_MC.D2_PT_3 ;
  wire \NlwInverterSignal_outreg<0>_MC.D2_PT_0/IN7 ;
  wire \NlwInverterSignal_outreg<0>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_outreg<0>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_outreg<0>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal__n010237_MC.D2_PT_0/IN7 ;
  wire \NlwInverterSignal__n010237_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal__n010237_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal__n010237_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal__n010237_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal__n010237_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal__n010237_MC.D2_PT_6/IN0 ;
  wire \NlwInverterSignal_N_PZ_96_MC.D1/IN6 ;
  wire \NlwInverterSignal_outreg<1>_MC.D2_PT_1/IN7 ;
  wire \NlwInverterSignal_outreg<1>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_outreg<1>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_outreg<2>_MC.D2_PT_1/IN7 ;
  wire \NlwInverterSignal_outreg<2>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_outreg<2>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_outreg<3>_MC.D2_PT_0/IN7 ;
  wire \NlwInverterSignal_outreg<3>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_outreg<3>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_outreg<3>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal__n009837_MC.D2_PT_0/IN7 ;
  wire \NlwInverterSignal__n009837_MC.D2_PT_1/IN6 ;
  wire \NlwInverterSignal__n009837_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal__n009837_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal__n009837_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal__n009837_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal__n009837_MC.D2_PT_6/IN0 ;
  wire \NlwInverterSignal_N_PZ_98_MC.D1/IN4 ;
  wire \NlwInverterSignal_outreg<4>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_outreg<4>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outreg<4>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outreg<5>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_outreg<5>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_outreg<5>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_FOOBAR1__ctinst/4/IN0 ;
  wire \NlwInverterSignal_FOOBAR1__ctinst/4/IN1 ;
  wire \NlwInverterSignal_FOOBAR2__ctinst/4/IN0 ;
  wire \NlwInverterSignal_FOOBAR2__ctinst/4/IN1 ;
  wire [5 : 0] outreg;
  initial $sdf_annotate("keypadscan_timesim.sdf");
  X_IPAD \clk.PAD  (
    .PAD(clk)
  );
  X_BUF \clk_II/FCLK_0  (
    .I(clk),
    .O(\clk_II/FCLK )
  );
  X_IPAD \column<0>.PAD  (
    .PAD(column[0])
  );
  X_BUF \column<0>_II/UIM_1  (
    .I(column[0]),
    .O(\column<0>_II/UIM )
  );
  X_IPAD \column<1>.PAD  (
    .PAD(column[1])
  );
  X_BUF \column<1>_II/UIM_2  (
    .I(column[1]),
    .O(\column<1>_II/UIM )
  );
  X_IPAD \column<2>.PAD  (
    .PAD(column[2])
  );
  X_BUF \column<2>_II/UIM_3  (
    .I(column[2]),
    .O(\column<2>_II/UIM )
  );
  X_IPAD \column<3>.PAD  (
    .PAD(column[3])
  );
  X_BUF \column<3>_II/UIM_4  (
    .I(column[3]),
    .O(\column<3>_II/UIM )
  );
  X_IPAD \column<4>.PAD  (
    .PAD(column[4])
  );
  X_BUF \column<4>_II/UIM_5  (
    .I(column[4]),
    .O(\column<4>_II/UIM )
  );
  X_IPAD \column<5>.PAD  (
    .PAD(column[5])
  );
  X_BUF \column<5>_II/UIM_6  (
    .I(column[5]),
    .O(\column<5>_II/UIM )
  );
  X_IPAD \column<6>.PAD  (
    .PAD(column[6])
  );
  X_BUF \column<6>_II/UIM_7  (
    .I(column[6]),
    .O(\column<6>_II/UIM )
  );
  X_IPAD \column<7>.PAD  (
    .PAD(column[7])
  );
  X_BUF \column<7>_II/UIM_8  (
    .I(column[7]),
    .O(\column<7>_II/UIM )
  );
  X_OPAD \out<0>.PAD  (
    .PAD(out[0])
  );
  X_BUF \out<0>  (
    .I(\out<0>_MC.Q ),
    .O(out[0])
  );
  X_OPAD \out<1>.PAD  (
    .PAD(out[1])
  );
  X_BUF \out<1>  (
    .I(\out<1>_MC.Q ),
    .O(out[1])
  );
  X_OPAD \out<2>.PAD  (
    .PAD(out[2])
  );
  X_BUF \out<2>  (
    .I(\out<2>_MC.Q ),
    .O(out[2])
  );
  X_OPAD \out<3>.PAD  (
    .PAD(out[3])
  );
  X_BUF \out<3>  (
    .I(\out<3>_MC.Q ),
    .O(out[3])
  );
  X_OPAD \out<4>.PAD  (
    .PAD(out[4])
  );
  X_BUF \out<4>  (
    .I(\out<4>_MC.Q ),
    .O(out[4])
  );
  X_OPAD \out<5>.PAD  (
    .PAD(out[5])
  );
  X_BUF \out<5>  (
    .I(\out<5>_MC.Q ),
    .O(out[5])
  );
  X_OPAD \row<0>.PAD  (
    .PAD(row[0])
  );
  X_BUF \row<0>  (
    .I(\row<0>_MC.Q ),
    .O(row[0])
  );
  X_OPAD \row<1>.PAD  (
    .PAD(row[1])
  );
  X_BUF \row<1>  (
    .I(\row<1>_MC.Q ),
    .O(row[1])
  );
  X_OPAD \row<2>.PAD  (
    .PAD(row[2])
  );
  X_BUF \row<2>  (
    .I(\row<2>_MC.Q ),
    .O(row[2])
  );
  X_OPAD \row<3>.PAD  (
    .PAD(row[3])
  );
  X_BUF \row<3>  (
    .I(\row<3>_MC.Q ),
    .O(row[3])
  );
  X_OPAD \row<4>.PAD  (
    .PAD(row[4])
  );
  X_BUF \row<4>  (
    .I(\row<4>_MC.Q ),
    .O(row[4])
  );
  X_OPAD \row<5>.PAD  (
    .PAD(row[5])
  );
  X_BUF \row<5>  (
    .I(\row<5>_MC.Q ),
    .O(row[5])
  );
  X_OPAD \row<6>.PAD  (
    .PAD(row[6])
  );
  X_BUF \row<6>  (
    .I(\row<6>_MC.Q ),
    .O(row[6])
  );
  X_OPAD \row<7>.PAD  (
    .PAD(row[7])
  );
  X_BUF \row<7>  (
    .I(\row<7>_MC.Q ),
    .O(row[7])
  );
  X_BUF \out<0>_MC.Q_9  (
    .I(\out<0>_MC.Q_tsimrenamed_net_ ),
    .O(\out<0>_MC.Q )
  );
  X_BUF \out<0>_MC.Q_tsimrenamed_net__10  (
    .I(\out<0>_MC.D ),
    .O(\out<0>_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \out<0>_MC.D_11  (
    .I0(\out<0>_MC.D1 ),
    .I1(\out<0>_MC.D2 ),
    .O(\out<0>_MC.D )
  );
  X_ZERO \out<0>_MC.D1_12  (
    .O(\out<0>_MC.D1 )
  );
  X_AND2 \out<0>_MC.D2_PT_0_13  (
    .I0(outreg[0]),
    .I1(outreg[0]),
    .O(\out<0>_MC.D2_PT_0 )
  );
  X_AND8 \out<0>_MC.D2_PT_1_14  (
    .I0(\column<0>_II/UIM ),
    .I1(\column<1>_II/UIM ),
    .I2(\column<2>_II/UIM ),
    .I3(\column<3>_II/UIM ),
    .I4(\column<4>_II/UIM ),
    .I5(\column<5>_II/UIM ),
    .I6(\column<6>_II/UIM ),
    .I7(\column<7>_II/UIM ),
    .O(\out<0>_MC.D2_PT_1 )
  );