keypadscan.syr

适用于FPGA的SOPC方面的元器件添加

Release 6.3.03i - xst G.38
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: KeypadScan.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : KeypadScan.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : KeypadScan
Output Format                      : NGC
Target Device                      : xbr

---- Source Options
Top Module Name                    : KeypadScan
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : KeypadScan.lso
verilog2001                        : YES
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "KeypadScan.v"
Module <KeypadScan> compiled
No errors in compilation
Analysis of file <KeypadScan.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <KeypadScan>.
Module <KeypadScan> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <KeypadScan>.
    Related source file is KeypadScan.v.
WARNING:Xst:737 - Found 1-bit latch for signal <outreg_3>.
WARNING:Xst:737 - Found 1-bit latch for signal <outreg_4>.
WARNING:Xst:737 - Found 1-bit latch for signal <outreg_5>.
WARNING:Xst:737 - Found 1-bit latch for signal <outreg_0>.
WARNING:Xst:737 - Found 1-bit latch for signal <outreg_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <outreg_2>.
    Found 8-bit register for signal <shiftreg>.
Unit <KeypadScan> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 1
 8-bit register                    : 1
# Latches                          : 6
 1-bit latch                       : 6

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <KeypadScan> ...
  implementation constraint: INIT=s	 : shiftreg_7
  implementation constraint: INIT=s	 : shiftreg_6
  implementation constraint: INIT=r	 : shiftreg_0
  implementation constraint: INIT=s	 : shiftreg_1
  implementation constraint: INIT=s	 : shiftreg_2
  implementation constraint: INIT=s	 : shiftreg_3
  implementation constraint: INIT=s	 : shiftreg_4
  implementation constraint: INIT=s	 : shiftreg_5

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : KeypadScan.ngr
Top Level Output File Name         : KeypadScan
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : YES
Target Technology                  : xbr
Macro Preserve                     : YES
XOR Preserve                       : YES
Clock Enable                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 23

Macro Statistics :
# Registers                        : 8
#      1-bit register              : 8

Cell Usage :
# BELS                             : 186
#      AND2                        : 96
#      AND4                        : 14
#      AND8                        : 1
#      GND                         : 1
#      INV                         : 42
#      OR2                         : 24
#      XOR2                        : 8
# FlipFlops/Latches                : 14
#      FDCE                        : 8
#      LD                          : 6
# IO Buffers                       : 23
#      IBUF                        : 9
#      OBUF                        : 14
=========================================================================
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