📄 keypadscan.rpt
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column[3] && column[2] && column[1] && column[0])
|| (column[7] && column[6] && !column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0])
|| (!column[7] && column[6] && column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0]));
assign N_PZ_96 = (column[7] && !column[6] && column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0]);
assign out[1] = ((outreg[1])
|| (column[7] && column[6] && column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0]));
LDCP LDCP_outreg1 (outreg[1],outreg_D[1],!,1'b0,1'b0);
assign outreg_D[1] = ((N_PZ_96)
|| (column[7] && column[6] && column[5] && column[4] &&
column[3] && !column[2] && column[1] && column[0])
|| (column[7] && column[6] && column[5] && column[4] &&
!column[3] && column[2] && column[1] && column[0])
|| (!column[7] && column[6] && column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0]));
assign out[2] = ((outreg[2])
|| (column[7] && column[6] && column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0]));
LDCP LDCP_outreg2 (outreg[2],outreg_D[2],!,1'b0,1'b0);
assign outreg_D[2] = ((N_PZ_96)
|| (column[7] && column[6] && column[5] && !column[4] &&
column[3] && column[2] && column[1] && column[0])
|| (column[7] && column[6] && !column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0])
|| (!column[7] && column[6] && column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0]));
assign out[3] = ((outreg[3])
|| (column[7] && column[6] && column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0]));
LDCP LDCP_outreg3 (outreg[3],outreg_D[3],!,1'b0,1'b0);
assign outreg_D[3] = ((row[2] && row[3] && row[4] && row[5] && row[6] &&
row[7] && row[0] && !row[1])
|| (row[2] && row[3] && row[4] && row[5] && row[6] &&
!row[7] && row[0] && row[1])
|| (row[2] && row[3] && row[4] && !row[5] && row[6] &&
row[7] && row[0] && row[1])
|| (row[2] && !row[3] && row[4] && row[5] && row[6] &&
row[7] && row[0] && row[1]));
FDCPE FDCPE_row2 (row[2],row[1],clk,1'b0,1'b0,row_CE[2]);
assign row_CE[2] = (column[7] && column[6] && column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0]);
FDCPE FDCPE_row1 (row[1],row[0],clk,1'b0,1'b0,row_CE[1]);
assign row_CE[1] = (column[7] && column[6] && column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0]);
FDCPE FDCPE_row0 (row[0],row[7],clk,1'b0,1'b0,row_CE[0]);
assign row_CE[0] = (column[7] && column[6] && column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0]);
FDCPE FDCPE_row7 (row[7],row[6],clk,1'b0,1'b0,row_CE[7]);
assign row_CE[7] = (column[7] && column[6] && column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0]);
FDCPE FDCPE_row6 (row[6],row[5],clk,1'b0,1'b0,row_CE[6]);
assign row_CE[6] = (column[7] && column[6] && column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0]);
FDCPE FDCPE_row5 (row[5],row[4],clk,1'b0,1'b0,row_CE[5]);
assign row_CE[5] = (column[7] && column[6] && column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0]);
FDCPE FDCPE_row4 (row[4],row[3],clk,1'b0,1'b0,row_CE[4]);
assign row_CE[4] = (column[7] && column[6] && column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0]);
FDCPE FDCPE_row3 (row[3],row[2],clk,1'b0,1'b0,row_CE[3]);
assign row_CE[3] = (column[7] && column[6] && column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0]);
assign _n009837 = ((row[2] && row[3] && row[4] && row[5] && row[6] &&
row[7] && row[0] && !row[1])
|| (row[2] && row[3] && row[4] && row[5] && row[6] &&
row[7] && !row[0] && row[1])
|| (row[2] && row[3] && row[4] && row[5] && row[6] &&
!row[7] && row[0] && row[1])
|| (row[2] && row[3] && row[4] && !row[5] && row[6] &&
row[7] && row[0] && row[1])
|| (row[2] && row[3] && !row[4] && row[5] && row[6] &&
row[7] && row[0] && row[1])
|| (row[2] && !row[3] && row[4] && row[5] && row[6] &&
row[7] && row[0] && row[1])
|| (!row[2] && row[3] && row[4] && row[5] && row[6] &&
row[7] && row[0] && row[1]));
assign N_PZ_98 = (row[2] && row[3] && row[4] && row[5] && !row[6] &&
row[7] && row[0] && row[1]);
assign out[4] = ((outreg[4])
|| (column[7] && column[6] && column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0]));
LDCP LDCP_outreg4 (outreg[4],outreg_D[4],!,1'b0,1'b0);
assign outreg_D[4] = ((N_PZ_98)
|| (row[2] && row[3] && row[4] && row[5] && row[6] &&
!row[7] && row[0] && row[1])
|| (row[2] && !row[3] && row[4] && row[5] && row[6] &&
row[7] && row[0] && row[1])
|| (!row[2] && row[3] && row[4] && row[5] && row[6] &&
row[7] && row[0] && row[1]));
assign out[5] = ((outreg[5])
|| (column[7] && column[6] && column[5] && column[4] &&
column[3] && column[2] && column[1] && column[0]));
LDCP LDCP_outreg5 (outreg[5],outreg_D[5],!,1'b0,1'b0);
assign outreg_D[5] = ((N_PZ_98)
|| (row[2] && row[3] && row[4] && row[5] && row[6] &&
!row[7] && row[0] && row[1])
|| (row[2] && row[3] && row[4] && !row[5] && row[6] &&
row[7] && row[0] && row[1])
|| (row[2] && row[3] && !row[4] && row[5] && row[6] &&
row[7] && row[0] && row[1]));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FDDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
FTDCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
**************************** Device Pin Out ****************************
Device : XC2C32A-6-CP56
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/ \
1| o o o o o o o o o o |
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2| o o |
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3| o o o o o o o o |
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4| o o o o |
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5| o o o o |
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6| o o o o |
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7| o o o o |
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8| o o o o o o o o |
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9| o o |
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10| o o o o o o o o o o |
\_________________________________________/
A B C D E F G H J K
Pin Signal Pin Signal
No. Name No. Name
A1 out<0> F1 row<0>
A2 row<6> F3 out<2>
A3 row<5> F8 GND
A4 NC F10 WPU
A5 NC G1 out<1>
A6 TDO G3 out<4>
A7 NC G8 VCC
A8 NC G10 WPU
A9 NC H1 out<3>
A10 column<3> H3 WPU
B1 row<7> H4 GND
B10 column<4> H5 WPU
C1 row<4> H6 VCCIO-1.8
C3 NC H7 NC
C4 column<0> H8 WPU
C5 column<1> H10 WPU
C6 VCCIO-1.8 J1 clk
C7 GND J10 TDI
C8 column<2> K1 out<5>
C10 column<5> K2 column<7>
D1 row<3> K3 WPU
D3 VCCAUX K4 NC
D8 NC K5 WPU
D10 WPU K6 NC
E1 row<2> K7 NC
E3 row<1> K8 WPU
E8 column<6> K9 TMS
E10 NC K10 TCK
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
KPR = Unused I/O with weak keeper (leave unconnected)
WPU = Unused I/O with weak pull up (leave unconnected)
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
VCCAUX = Power supply for JTAG pins
VCCIO-3.3 = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
VCCIO-2.5 = I/O supply voltage for LVCMOS25, SSTL2_I
VCCIO-1.8 = I/O supply voltage for LVCMOS18
VCCIO-1.5 = I/O supply voltage for LVCMOS15, HSTL_I
VREF = Reference voltage for indicated input standard
*VREF = Reference voltage pin selected by software
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc2c32a-6-CP56
Optimization Method : DENSITY
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Set Unused I/O Pin Termination : PULLUP
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Enable Input Registers : ON
Function Block Fan-in Limit : 38
Use DATA_GATE Attribute : ON
Set Tristate Outputs to Termination Mode : PULLUP
Default Voltage Standard for All Outputs : LVCMOS18
Input Limit : 32
Pterm Limit : 28
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