tb.asv

适用于FPGA的SOPC方面的元器件添加

/* This test bench simulates an 8x8 keypad by connecting each of the
8 row inputs to each of the 8 column outputs one at a time.  There
will be 64 different combinations of these connections which simulates
the pressing of 64 different keys of the 8x8 keypad.

Mike Gulotta, 3/4/05
*/
 
`timescale 1 ns / 1 ns

module KeypadScan_tb_v_tf();

// Inputs
    reg clk;
    wire [7:0] column;
    reg [11:0] count;
    reg [2:0] push;

// Outputs
    wire [5:0] out;
    wire [7:0] row;
    reg [7:0] r, c;

// Instantiate the UUT
    KeypadScan uut (
        .clk(clk),
        .out(out),       
        .row(row),       //input from UUT
        .column(column)  //output to UUT
        );

// Initialize Inputs
        initial begin
            clk = 0;
            count = 0;
        end

always begin
   forever
      #10000 clk = ~clk; // 50Khz.
end


always @(posedge clk) 
      count <= count + 1;


// Model 8x8, 64 key keypad...
always @(count[11:9], row)
   case (count[11:9])
      3'b000: r = {1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1, row[0] };
      3'b001: r = {1'b1,1'b1,1'b1,1'b1,1'b1,1'b1, row[1], 1'b1};
      3'b010: r = {1'b1,1'b1,1'b1,1'b1,1'b1, row[2], 1'b1,1'b1};
      3'b011: r = {1'b1,1'b1,1'b1,1'b1, row[3], 1'b1,1'b1,1'b1};
      3'b100: r = {1'b1,1'b1,1'b1, row[4] ,1'b1,1'b1,1'b1,1'b1};
      3'b101: r = {1'b1,1'b1, row[5], 1'b1,1'b1,1'b1,1'b1,1'b1};
      3'b110: r = {1'b1, row[6], 1'b1,1'b1,1'b1,1'b1,1'b1,1'b1};
      3'b111: r = { row[7], 1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1};
 endcase

always @(count[8:4], r) begin
   if (&count[5:4] == 1)
      c = {1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1};
   else begin
      casex (count[8:6])
         3'b000: c = {r[7],r[6],r[5],r[4],r[3],r[2],r[1],r[0]};
         3'b001: c = {r[6],r[5],r[4],r[3],r[2],r[1],r[0],r[7]};
         3'b010: c = {r[5],r[4],r[3],r[2],r[1],r[0],r[7],r[6]};
         3'b011: c = {r[4],r[3],r[2],r[1],r[0],r[7],r[6],r[5]};
         3'b100: c = {r[3],r[2],r[1],r[0],r[7],r[6],r[5],r[4]};
         3'b101: c = {r[2],r[1],r[0],r[7],r[6],r[5],r[4],r[3]};
         3'b110: c = {r[1],r[0],r[7],r[6],r[5],r[4],r[3],r[2]};
         3'b111: c = {r[0],r[7],r[6],r[5],r[4],r[3],r[2],r[1]};
      endcase
   end
end

assign column = c;

endmodule