rsynch-1-optimized.trt

一些简单的VHDL实例

=======================
Chip rsynch-1-Optimized
=======================

Summary Information:
--------------------
Type: Optimized implementation
Source: rsynch-1, up to date
Status: 0 errors, 0 warnings, 0 messages
Export: exported after last optimization

Target Information:
-------------------
Vendor: Altera
Family: MAX7000
Device: AUTO
Speed: FASTEST

Chip Parameters:
----------------
Optimize for: Speed
Optimization effort: High
Frequency: 50 MHz
Is module: No
Keep io pads: No
Number of flip-flops: 2
Number of latches: 0

Chip Design Hierarchy:
----------------------
rsynch: defined in E:\vhdl_tools\100Examples\TEMP\RSYNCH\rsynch.vhd

Primitive reference count:
--------------------------
DFFE          2
INV           1

Clocks:
-------
                           Required  Estimated                       
Period   Rise     Fall     Freq      Freq       Signal               
(ns)     (ns)     (ns)     (MHz)     (MHz)                           
...............................................................
 20        0       10       50.00     -1.00     default              
 -1       -1       -1      -1000.00  100.00     clk                  

Timing Groups:
--------------
                                                              
                                                              
Name                 Description                              
............................................................
(I)                  Input ports                              
(O)                  Output ports                             
(RC,clk)             Clocked by rising edge of clk            

Timing Path Groups:
-------------------
                                          Required   Estimated  
                                          Delay      Delay      
From                 To                   (ns)       (ns)       
............................................................
(I)                  (RC,clk)              20.00       2.50     
(RC,clk)             (O)                   20.00       1.00     
(RC,clk)             (RC,clk)              20.00       3.00     

Input Port Timing:
------------------
                     Required   Estimated                       
Port                 Delay      Slack                           
Name                 (ns)       (ns)       To-Group             
............................................................
clk                   20.00      20.00     (RC,clk)             
reset                 17.50      17.50     (RC,clk)             
d                     18.00      18.00     (RC,clk)             
en                      n/a        n/a     (RC,clk)             

Output Port Timing:
-------------------
                     Required   Estimated                       
Port                 Delay      Slack                           
Name                 (ns)       (ns)       From-Group           
............................................................
q                     20.00      19.00     (RC,clk)             

Critical Path Timing:
---------------------
           Arrival    Required                                
Cell       Time       Time       Fanout                       
Type       (ns)       (ns)       Count   Pin-Name             
.........................................................
DFFE         3.00      20.00       2     /rsynch-1-Optimized/q
DFFE         1.00      18.00       1     /rsynch-1-Optimized/q
DFFE         1.00      18.00       1     /rsynch-1-Optimized/t
DFFE         0.00      17.00       2     /rsynch-1-Optimized/t