rsynch-1.trt

来自「一些简单的VHDL实例」· TRT 代码 · 共 84 行

=============
Chip rsynch-1
=============

Summary Information:
--------------------
Type: Initial implementation
Source: out-of-date
Status: 0 errors, 0 warnings, 1 messages

Target Information:
-------------------
Vendor: Altera
Family: MAX7000
Device: AUTO
Speed: FASTEST

Chip Parameters:
----------------
Optimize for: Speed
Optimization effort: High
Frequency: 50 MHz
Is module: No
Keep io pads: No
Number of flip-flops: 0
Number of latches: 0

Chip Design Hierarchy:
----------------------
rsynch: defined in E:\vhdl_tools\100Examples\TEMP\RSYNCH\rsynch.vhd

Primitive reference count:
--------------------------
SEQ           2

Clocks:
-------
                           Required  Estimated                       
Period   Rise     Fall     Freq      Freq       Signal               
(ns)     (ns)     (ns)     (MHz)     (MHz)                           
...............................................................
 20        0       10       50.00     -1.00     default              
 -1       -1       -1      -1000.00  100.00     clk                  

Timing Groups:
--------------
                                                              
                                                              
Name                 Description                              
............................................................
(I)                  Input ports                              
(O)                  Output ports                             
(RC,clk)             Clocked by rising edge of clk            

Timing Path Groups:
-------------------
                                          Required   Estimated  
                                          Delay      Delay      
From                 To                   (ns)       (ns)       
............................................................
(I)                  (RC,clk)              20.00      -1.00     
(RC,clk)             (O)                   20.00      -1.00     
(RC,clk)             (RC,clk)              20.00      -1.00     

Input Port Timing:
------------------
                     Required   Estimated                       
Port                 Delay      Slack                           
Name                 (ns)       (ns)       To-Group             
............................................................
clk                   20.00      -1.00     (RC,clk)             
reset                 20.00      -1.00     (RC,clk)             
d                     20.00      -1.00     (RC,clk)             
en                    20.00      -1.00     (RC,clk)             

Output Port Timing:
-------------------
                     Required   Estimated                       
Port                 Delay      Slack                           
Name                 (ns)       (ns)       From-Group           
............................................................
q                     20.00      -1.00     (RC,clk)