rsynch.out

一些简单的VHDL实例

Inferred memory devices in process 'P1'
	in routine rsynch line 11 in file
         'E:/vhdl_tools/100Examples/TEMP/RSYNCH/rsynch.vhd'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|        q_reg        | Flip-flop |   1   |  -  | -  | Y  | N  | N  | N  | N  |
|      temp_reg       | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
===============================================================================

q_reg
-----
    Async-reset: reset


temp_reg
--------
    set/reset/toggle: none


Writing to hnl file 'E:\vhdl_tools\100Examples\TEMP/RSYNCH/workdirs/WORK/rsynch.hnl'