📄 busis.trt
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==========
Chip busis
==========
Summary Information:
--------------------
Type: Initial implementation
Source: out-of-date
Status: 0 errors, 17 warnings, 1 messages
Target Information:
-------------------
Vendor: Altera
Family: FLEX10K
Device: AUTO
Speed: FASTEST
Chip Parameters:
----------------
Optimize for: Speed
Optimization effort: High
Frequency: 50 MHz
Is module: No
Keep io pads: No
Number of flip-flops: 0
Number of latches: 0
Chip Design Hierarchy:
----------------------
busis: defined in G:\Documents and Settings\hejianbin\My Documents\vhdl\busis.vhd
Primitive reference count:
--------------------------
AND 176
SEQ 56
TRI 32
Clocks:
-------
Required Estimated
Period Rise Fall Freq Freq Signal
(ns) (ns) (ns) (MHz) (MHz)
...............................................................
20 0 10 50.00 -1.00 default
-1 -1 -1 -1000.00 100.00 wr
-1 -1 -1 -1000.00 100.00 cs
-1 -1 -1 -1000.00 100.00 N164
-1 -1 -1 -1000.00 100.00 N156
-1 -1 -1 -1000.00 100.00 rd
-1 -1 -1 -1000.00 100.00 N157
Timing Groups:
--------------
Name Description
............................................................
(I) Input ports
(O) Output ports
(RC,wr) Clocked by rising edge of wr
(LL,wr) Latched by low-value of wr
(HL,cs) Latched by high-value of cs
(LL,cs) Latched by low-value of cs
(LL,N164) Latched by low-value of N164
(LL,N156) Latched by low-value of N156
(HL,rd) Latched by high-value of rd
(LL,rd) Latched by low-value of rd
(LL,N157) Latched by low-value of N157
Timing Path Groups:
-------------------
Required Estimated
Delay Delay
From To (ns) (ns)
............................................................
(I) (O) 20.00 -1.00
(I) (RC,wr) 20.00 -1.00
(RC,wr) (O) 20.00 -1.00
(RC,wr) (RC,wr) 20.00 -1.00
(LL,wr) (RC,wr) 20.00 -1.00
(HL,cs) (O) 10.00 -1.00
(LL,cs) (O) 20.00 -1.00
(LL,cs) (RC,wr) 20.00 -1.00
(LL,N164) (O) 20.00 -1.00
(LL,N156) (O) 20.00 -1.00
(HL,rd) (O) 10.00 -1.00
(LL,rd) (O) 20.00 -1.00
(LL,N157) (O) 20.00 -1.00
Input Port Timing:
------------------
Required Estimated
Port Delay Slack
Name (ns) (ns) To-Group
............................................................
reset 20.00 -1.00 (RC,wr)
rd 20.00 -1.00 (RC,wr)
wr 20.00 -1.00 (RC,wr)
cs 20.00 -1.00 (RC,wr)
a0 20.00 -1.00 (RC,wr)
a1 20.00 -1.00 (RC,wr)
pa7 20.00 -1.00 (RC,wr)
pa6 20.00 -1.00 (RC,wr)
pa5 20.00 -1.00 (RC,wr)
pa4 20.00 -1.00 (RC,wr)
pa3 20.00 -1.00 (RC,wr)
pa2 20.00 -1.00 (RC,wr)
pa1 20.00 -1.00 (RC,wr)
pa0 20.00 -1.00 (RC,wr)
pb7 20.00 -1.00 (RC,wr)
pb6 20.00 -1.00 (RC,wr)
pb5 20.00 -1.00 (RC,wr)
pb4 20.00 -1.00 (RC,wr)
pb3 20.00 -1.00 (RC,wr)
pb2 20.00 -1.00 (RC,wr)
pb1 20.00 -1.00 (RC,wr)
pb0 20.00 -1.00 (RC,wr)
pcl3 20.00 -1.00 (RC,wr)
pcl2 20.00 -1.00 (RC,wr)
pcl1 20.00 -1.00 (RC,wr)
pcl0 20.00 -1.00 (RC,wr)
pch3 20.00 -1.00 (RC,wr)
pch2 20.00 -1.00 (RC,wr)
pch1 20.00 -1.00 (RC,wr)
pch0 20.00 -1.00 (RC,wr)
d7 20.00 -1.00 (RC,wr)
d6 20.00 -1.00 (RC,wr)
d5 20.00 -1.00 (RC,wr)
d4 20.00 -1.00 (RC,wr)
d3 20.00 -1.00 (RC,wr)
d2 20.00 -1.00 (RC,wr)
d1 20.00 -1.00 (RC,wr)
d0 20.00 -1.00 (RC,wr)
Output Port Timing:
-------------------
Required Estimated
Port Delay Slack
Name (ns) (ns) From-Group
............................................................
pa7 20.00 -1.00 (RC,wr)
pa6 20.00 -1.00 (RC,wr)
pa5 20.00 -1.00 (RC,wr)
pa4 20.00 -1.00 (RC,wr)
pa3 20.00 -1.00 (RC,wr)
pa2 20.00 -1.00 (RC,wr)
pa1 20.00 -1.00 (RC,wr)
pa0 20.00 -1.00 (RC,wr)
pb7 20.00 -1.00 (RC,wr)
pb6 20.00 -1.00 (RC,wr)
pb5 20.00 -1.00 (RC,wr)
pb4 20.00 -1.00 (RC,wr)
pb3 20.00 -1.00 (RC,wr)
pb2 20.00 -1.00 (RC,wr)
pb1 20.00 -1.00 (RC,wr)
pb0 20.00 -1.00 (RC,wr)
pcl3 20.00 -1.00 (RC,wr)
pcl2 20.00 -1.00 (RC,wr)
pcl1 20.00 -1.00 (RC,wr)
pcl0 20.00 -1.00 (RC,wr)
pch3 20.00 -1.00 (RC,wr)
pch2 20.00 -1.00 (RC,wr)
pch1 20.00 -1.00 (RC,wr)
pch0 20.00 -1.00 (RC,wr)
d7 20.00 -1.00 (RC,wr)
d6 20.00 -1.00 (RC,wr)
d5 20.00 -1.00 (RC,wr)
d4 20.00 -1.00 (RC,wr)
d3 20.00 -1.00 (RC,wr)
d2 20.00 -1.00 (RC,wr)
d1 20.00 -1.00 (RC,wr)
d0 20.00 -1.00 (RC,wr)
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