count60.trt

一些简单的VHDL实例

============
Chip count60
============

Summary Information:
--------------------
Type: Initial implementation
Source: out-of-date
Status: 0 errors, 1 warnings, 1 messages

Target Information:
-------------------
Vendor: Altera
Family: MAX7000
Device: AUTO
Speed: FASTEST

Chip Parameters:
----------------
Optimize for: Speed
Optimization effort: High
Frequency: 50 MHz
Is module: No
Keep io pads: No
Number of flip-flops: 0
Number of latches: 0

Chip Design Hierarchy:
----------------------
count60: defined in G:\Documents and Settings\hejianbin\My Documents\vhdl\count60.vhd

Primitive reference count:
--------------------------
*ADD_TC_OP_3_3_3    1
*ADD_TC_OP_4_4_4    1
*SELECT_OP_2.3_2.1_3    1
*SELECT_OP_2.4_2.1_4    1
AND          18
SEQ           7

Clocks:
-------
                           Required  Estimated                       
Period   Rise     Fall     Freq      Freq       Signal               
(ns)     (ns)     (ns)     (MHz)     (MHz)                           
...............................................................
 20        0       10       50.00     -1.00     default              
 -1       -1       -1      -1000.00  100.00     clk                  
 -1       -1       -1      -1000.00  100.00     bcd1wr               
 -1       -1       -1      -1000.00  100.00     bcd10wr              

Timing Groups:
--------------
                                                              
                                                              
Name                 Description                              
............................................................
(I)                  Input ports                              
(O)                  Output ports                             
(RC,clk)             Clocked by rising edge of clk            
(HL,bcd1wr)          Latched by high-value of bcd1wr          
(LL,bcd1wr)          Latched by low-value of bcd1wr           
(HL,bcd10wr)         Latched by high-value of bcd10wr         
(LL,bcd10wr)         Latched by low-value of bcd10wr          

Timing Path Groups:
-------------------
                                          Required   Estimated  
                                          Delay      Delay      
From                 To                   (ns)       (ns)       
............................................................
(I)                  (O)                   20.00      -1.00     
(I)                  (RC,clk)              20.00      -1.00     
(I)                  (HL,bcd1wr)           10.00      -1.00     
(I)                  (LL,bcd1wr)           20.00      -1.00     
(I)                  (HL,bcd10wr)          10.00      -1.00     
(I)                  (LL,bcd10wr)          20.00      -1.00     
(RC,clk)             (O)                   20.00      -1.00     
(RC,clk)             (RC,clk)              20.00      -1.00     
(RC,clk)             (HL,bcd1wr)           10.00      -1.00     
(RC,clk)             (LL,bcd1wr)           20.00      -1.00     
(RC,clk)             (HL,bcd10wr)          10.00      -1.00     
(RC,clk)             (LL,bcd10wr)          20.00      -1.00     
(HL,bcd1wr)          (O)                   10.00      -1.00     
(HL,bcd1wr)          (RC,clk)              10.00      -1.00     
(HL,bcd1wr)          (HL,bcd1wr)           20.00      -1.00     
(HL,bcd1wr)          (LL,bcd1wr)           10.00      -1.00     
(HL,bcd1wr)          (HL,bcd10wr)          20.00      -1.00     
(HL,bcd1wr)          (LL,bcd10wr)          10.00      -1.00     
(LL,bcd1wr)          (O)                   20.00      -1.00     
(LL,bcd1wr)          (RC,clk)              20.00      -1.00     
(LL,bcd1wr)          (LL,bcd1wr)           20.00      -1.00     
(LL,bcd1wr)          (HL,bcd10wr)          10.00      -1.00     
(HL,bcd10wr)         (O)                   10.00      -1.00     
(HL,bcd10wr)         (RC,clk)              10.00      -1.00     
(HL,bcd10wr)         (HL,bcd1wr)           20.00      -1.00     
(HL,bcd10wr)         (LL,bcd1wr)           10.00      -1.00     
(HL,bcd10wr)         (HL,bcd10wr)          20.00      -1.00     
(HL,bcd10wr)         (LL,bcd10wr)          10.00      -1.00     
(LL,bcd10wr)         (O)                   20.00      -1.00     
(LL,bcd10wr)         (RC,clk)              20.00      -1.00     
(LL,bcd10wr)         (HL,bcd1wr)           10.00      -1.00     
(LL,bcd10wr)         (LL,bcd1wr)           20.00      -1.00     
(LL,bcd10wr)         (HL,bcd10wr)          10.00      -1.00     
(LL,bcd10wr)         (LL,bcd10wr)          20.00      -1.00     

Input Port Timing:
------------------
                     Required   Estimated                       
Port                 Delay      Slack                           
Name                 (ns)       (ns)       To-Group             
............................................................
clk                   20.00      -1.00     (RC,clk)             
bcd1wr                20.00      -1.00     (RC,clk)             
bcd10wr               20.00      -1.00     (RC,clk)             
cin                   20.00      -1.00     (RC,clk)             
datain3               20.00      -1.00     (RC,clk)             
datain2               20.00      -1.00     (RC,clk)             
datain1               20.00      -1.00     (RC,clk)             
datain0               20.00      -1.00     (RC,clk)             

Output Port Timing:
-------------------
                     Required   Estimated                       
Port                 Delay      Slack                           
Name                 (ns)       (ns)       From-Group           
............................................................
co                    20.00      -1.00     (RC,clk)             
bcd13                 20.00      -1.00     (RC,clk)             
bcd12                 20.00      -1.00     (RC,clk)             
bcd11                 20.00      -1.00     (RC,clk)             
bcd10                 20.00      -1.00     (RC,clk)             
bcd102                20.00      -1.00     (RC,clk)             
bcd101                20.00      -1.00     (RC,clk)             
bcd100                20.00      -1.00     (RC,clk)