temp1.out

来自「一些简单的VHDL实例」· OUT 代码 · 共 37 行

Warning: Variable 'y2' is being read 
	in routine temp1 line 10 in file 'E:/vhdl_tools/100Examples/TEMP/hjb/temp1.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)
Warning: Variable 'yq2' is being read 
	in routine temp1 line 10 in file 'E:/vhdl_tools/100Examples/TEMP/hjb/temp1.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)

Inferred memory devices in process 
	in routine temp1 line 10 in file
         'E:/vhdl_tools/100Examples/TEMP/hjb/temp1.vhd'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       y2_reg        | Flip-flop |   1   |  -  | -  | Y  | Y  | N  | N  | Y  |
|       yq2_reg       | Flip-flop |   1   |  -  | -  | Y  | Y  | N  | N  | Y  |
===============================================================================

y2_reg
------
    Async-reset: clr
    Async-set: pest
    Sync-toggle: n_2' n_4' n_5
    Async-set and Async-reset ==> Q: 1


yq2_reg
-------
    Async-reset: pest
    Async-set: clr
    Sync-toggle: n_2' n_4' n_5
    Async-set and Async-reset ==> Q: 0


Writing to hnl file 'E:\vhdl_tools\100Examples\TEMP\hjb/workdirs/WORK/temp1.hnl'