busis.out

一些简单的VHDL实例

Warning: Variable 'conreg' is being read 
	in routine busis line 25 in file 'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)
Warning: Variable 'a0' is being read 
	in routine busis line 25 in file 'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)
Warning: Variable 'pcl' is being read 
	in routine busis line 25 in file 'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)
Warning: Variable 'pb' is being read 
	in routine busis line 25 in file 'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)
Warning: Variable 'internal_bus_in' is being read 
	in routine busis line 25 in file 'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)
Warning: Variable 'a1' is being read 
	in routine busis line 25 in file 'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)
Warning: Variable 'pa' is being read 
	in routine busis line 25 in file 'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)
Warning: Variable 'st' is being read 
	in routine busis line 25 in file 'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)
Warning: Variable 'pch' is being read 
	in routine busis line 25 in file 'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)
Warning: Variable 'a1' is being read 
	in routine busis line 47 in file 'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)
Warning: Variable 'a0' is being read 
	in routine busis line 47 in file 'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)
Warning: Variable 'd' is being read 
	in routine busis line 47 in file 'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)
Warning: Variable 'conreg' is being read 
	in routine busis line 97 in file 'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)
Warning: Variable 'conreg' is being read 
	in routine busis line 106 in file 'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)
Warning: Variable 'conreg' is being read 
	in routine busis line 115 in file 'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)
Warning: Variable 'conreg' is being read 
	in routine busis line 123 in file 'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)

Inferred memory devices in process 
	in routine busis line 25 in file
         'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| internal_bus_in_reg |   Latch   |   8   |  N  | N  | ?  | ?  | -  | -  | -  |
| internal_bus_in_tri_enable_reg | Latch | 8 | N | N | ?  | ?  | -  | -  | -  |
===============================================================================

Inferred THREE-STATE control devices in process 
	in routine busis line 25 in
         file 'G:/Documents and Settings/hejianbin/My
         Documents/vhdl/busis.vhd'.
============================================================================
|     Three-state Device Name      |               Type               | MB |
============================================================================
|       internal_bus_in_tri7       |        Three-state Buffer        | N  |
|       internal_bus_in_tri0       |        Three-state Buffer        | N  |
|       internal_bus_in_tri1       |        Three-state Buffer        | N  |
|       internal_bus_in_tri6       |        Three-state Buffer        | N  |
|       internal_bus_in_tri4       |        Three-state Buffer        | N  |
|       internal_bus_in_tri3       |        Three-state Buffer        | N  |
|       internal_bus_in_tri2       |        Three-state Buffer        | N  |
|       internal_bus_in_tri5       |        Three-state Buffer        | N  |
| internal_bus_in_tri_enable_reg4  |         Latch (width 1)          | N  |
| internal_bus_in_tri_enable_reg3  |         Latch (width 1)          | N  |
| internal_bus_in_tri_enable_reg2  |         Latch (width 1)          | N  |
| internal_bus_in_tri_enable_reg5  |         Latch (width 1)          | N  |
| internal_bus_in_tri_enable_reg7  |         Latch (width 1)          | N  |
| internal_bus_in_tri_enable_reg0  |         Latch (width 1)          | N  |
| internal_bus_in_tri_enable_reg1  |         Latch (width 1)          | N  |
| internal_bus_in_tri_enable_reg6  |         Latch (width 1)          | N  |
============================================================================

internal_bus_in_reg2
--------------------
    reset/set: none


internal_bus_in_reg5
--------------------
    reset/set: none


internal_bus_in_reg4
--------------------
    reset/set: none


internal_bus_in_reg3
--------------------
    reset/set: none


internal_bus_in_reg1
--------------------
    reset/set: none


internal_bus_in_reg6
--------------------
    reset/set: none


internal_bus_in_reg7
--------------------
    reset/set: none


internal_bus_in_reg0
--------------------
    reset/set: none


internal_bus_in_tri_enable_reg4
-------------------------------
    reset/set: none


internal_bus_in_tri_enable_reg3
-------------------------------
    reset/set: none


internal_bus_in_tri_enable_reg2
-------------------------------
    reset/set: none


internal_bus_in_tri_enable_reg5
-------------------------------
    reset/set: none


internal_bus_in_tri_enable_reg7
-------------------------------
    reset/set: none


internal_bus_in_tri_enable_reg0
-------------------------------
    reset/set: none


internal_bus_in_tri_enable_reg1
-------------------------------
    reset/set: none


internal_bus_in_tri_enable_reg6
-------------------------------
    reset/set: none



Inferred memory devices in process 
	in routine busis line 47 in file
         'G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       ad_reg        |   Latch   |   2   |  Y  | N  | N  | N  | -  | -  | -  |
|     conreg_reg      | Flip-flop |   5   |  N  | N  | ?  | ?  | ?  | ?  | ?  |
|     conregf_reg     |   Latch   |   1   |  -  | -  | N  | N  | -  | -  | -  |
| internal_bus_out_reg |  Latch   |   8   |  Y  | N  | N  | N  | -  | -  | -  |
|    pa_latch_reg     | Flip-flop |   8   |  Y  | N  | Y  | N  | N  | N  | N  |
|    pb_latch_reg     | Flip-flop |   8   |  Y  | N  | Y  | N  | N  | N  | N  |
|    pc_latch_reg     | Flip-flop |   8   |  N  | N  | ?  | ?  | ?  | ?  | ?  |
===============================================================================

ad_reg (width 2)
----------------
    reset/set: none


conreg_reg7
-----------
    Async-set: reset


conreg_reg0
-----------
    Async-set: reset


conreg_reg1
-----------
    Async-set: reset


conreg_reg4
-----------
    Async-set: reset


conreg_reg3
-----------
    Async-set: reset


conregf_reg
-----------
    reset/set: none


internal_bus_out_reg (width 8)
------------------------------
    reset/set: none


pa_latch_reg (width 8)
----------------------
    Async-reset: reset


pb_latch_reg (width 8)
----------------------
    Async-reset: reset


pc_latch_reg0
-------------
    Async-reset: reset


pc_latch_reg7
-------------
    Async-reset: reset


pc_latch_reg6
-------------
    Async-reset: reset


pc_latch_reg1
-------------
    Async-reset: reset


pc_latch_reg3
-------------
    Async-reset: reset


pc_latch_reg4
-------------
    Async-reset: reset


pc_latch_reg5
-------------
    Async-reset: reset


pc_latch_reg2
-------------
    Async-reset: reset



Inferred THREE-STATE control devices in process 
	in routine busis line 97 in
         file 'G:/Documents and Settings/hejianbin/My
         Documents/vhdl/busis.vhd'.
============================================================================
|     Three-state Device Name      |               Type               | MB |
============================================================================
|             pa_tri4              |        Three-state Buffer        | N  |
|             pa_tri3              |        Three-state Buffer        | N  |
|             pa_tri2              |        Three-state Buffer        | N  |
|             pa_tri5              |        Three-state Buffer        | N  |
|             pa_tri7              |        Three-state Buffer        | N  |
|             pa_tri0              |        Three-state Buffer        | N  |
|             pa_tri1              |        Three-state Buffer        | N  |
|             pa_tri6              |        Three-state Buffer        | N  |
============================================================================


Inferred THREE-STATE control devices in process 
	in routine busis line 106 in
         file 'G:/Documents and Settings/hejianbin/My
         Documents/vhdl/busis.vhd'.
============================================================================
|     Three-state Device Name      |               Type               | MB |
============================================================================
|             pb_tri7              |        Three-state Buffer        | N  |
|             pb_tri0              |        Three-state Buffer        | N  |
|             pb_tri1              |        Three-state Buffer        | N  |
|             pb_tri6              |        Three-state Buffer        | N  |
|             pb_tri4              |        Three-state Buffer        | N  |
|             pb_tri3              |        Three-state Buffer        | N  |
|             pb_tri2              |        Three-state Buffer        | N  |
|             pb_tri5              |        Three-state Buffer        | N  |
============================================================================


Inferred THREE-STATE control devices in process 
	in routine busis line 115 in
         file 'G:/Documents and Settings/hejianbin/My
         Documents/vhdl/busis.vhd'.
============================================================================
|     Three-state Device Name      |               Type               | MB |
============================================================================
|             pcl_tri2             |        Three-state Buffer        | N  |
|             pcl_tri3             |        Three-state Buffer        | N  |
|             pcl_tri1             |        Three-state Buffer        | N  |
|             pcl_tri0             |        Three-state Buffer        | N  |
============================================================================


Inferred THREE-STATE control devices in process 
	in routine busis line 123 in
         file 'G:/Documents and Settings/hejianbin/My
         Documents/vhdl/busis.vhd'.
============================================================================
|     Three-state Device Name      |               Type               | MB |
============================================================================
|             pch_tri1             |        Three-state Buffer        | N  |
|             pch_tri0             |        Three-state Buffer        | N  |
|             pch_tri2             |        Three-state Buffer        | N  |
|             pch_tri3             |        Three-state Buffer        | N  |
============================================================================

Warning: Latch inferred in design 'busis' read with
	'hdlin_check_no_latch'. (HDL-307)
Writing to hnl file 'E:\vhdl_tools\100Examples\TEMP\hjb/workdirs/WORK/busis.hnl'