nand2-optimized.trt

来自「一些简单的VHDL实例」· TRT 代码 · 共 93 行

====================
Chip NAND2-Optimized
====================

Summary Information:
--------------------
Type: Optimized implementation
Source: NAND2, out-of-date
Status: 0 errors, 0 warnings, 0 messages
Export: exported after last optimization

Target Information:
-------------------
Vendor: Altera
Family: MAX7000
Device: AUTO
Speed: FASTEST

Chip Parameters:
----------------
Optimize for: Speed
Optimization effort: High
Frequency: 50 MHz
Is module: No
Keep io pads: No
Number of flip-flops: 0
Number of latches: 0

Chip Design Hierarchy:
----------------------
NAND2: defined in E:\HJB\VHDL\nand2.vhd

Primitive reference count:
--------------------------
AND2          1
INV           1

Clocks:
-------
                           Required  Estimated                       
Period   Rise     Fall     Freq      Freq       Signal               
(ns)     (ns)     (ns)     (MHz)     (MHz)                           
...............................................................
 20        0       10       50.00     -1.00     default              

Timing Groups:
--------------
                                                              
                                                              
Name                 Description                              
............................................................
(I)                  Input ports                              
(O)                  Output ports                             

Timing Path Groups:
-------------------
                                          Required   Estimated  
                                          Delay      Delay      
From                 To                   (ns)       (ns)       
............................................................
(I)                  (O)                    1.00       6.50     

Input Port Timing:
------------------
                     Required   Estimated                       
Port                 Delay      Slack                           
Name                 (ns)       (ns)       To-Group             
............................................................
a                     -5.50      -5.50     (O)                  
b                     -5.50      -5.50     (O)                  

Output Port Timing:
-------------------
                     Required   Estimated                       
Port                 Delay      Slack                           
Name                 (ns)       (ns)       From-Group           
............................................................
Y                      1.00      -5.50     (I)                  

Critical Path Timing:
---------------------
           Arrival    Required                                
Cell       Time       Time       Fanout                       
Type       (ns)       (ns)       Count   Pin-Name             
.........................................................
port         6.50       1.00       0     /NAND2-Optimized/Y   
INV          6.50       1.00       0     /NAND2-Optimized/C0/A
INV          6.00       0.50       1     /NAND2-Optimized/C0/A
AND2         6.00       0.50       1     /NAND2-Optimized/C1/A
AND2         0.00      -5.50       1     /NAND2-Optimized/C1/I
port         0.00      -5.50       1     /NAND2-Optimized/b