anal.info

来自「一些简单的VHDL实例」· INFO 代码 · 共 10 行

file {
  .version = 1;
  entity {
    .name = "busis";
    .mra_file = "busis.mra";
    .arch = {"rtl"};
    .syn_files = {"BUSIS.syn", "BUSIS__RTL.syn"};
   }
}