📄 g711.rpt
字号:
Project Information c:\study\vhdl\codecs\g711.3\g711.rptMAX+plus II Compiler Report FileVersion 9.4 12/10/1999Compiled: 03/07/2002 21:52:58Copyright (C) 1988-1999 Altera CorporationAny megafunction design, and related net list (encrypted or decrypted),support information, device programming or simulation file, and any otherassociated documentation or information provided by Altera or a partnerunder Altera's Megafunction Partnership Program may be used only toprogram PLD devices (but not masked PLD devices) from Altera. Any otheruse of such megafunction design, net list, support information, deviceprogramming or simulation file, or any other related documentation orinformation is prohibited for any other purpose, including, but notlimited to modification, reverse engineering, de-compiling, or use withany other silicon devices, unless such use is explicitly licensed undera separate agreement with Altera or a megafunction partner. Title tothe intellectual property, including patents, copyrights, trademarks,trade secrets, or maskworks, embodied in any such megafunction design,net list, support information, device programming or simulation file, orany other related documentation or information provided by Altera or amegafunction partner, remains with Altera, the megafunction partner, ortheir respective licensors. No other licenses, including any licensesneeded under any third party's intellectual property, are provided herein.***** Project compilation was successfulG711** DEVICE SUMMARY **Chip/ Input Output Bidir Memory Memory LCsPOF Device Pins Pins Pins Bits % Utilized LCs % Utilizedg711 EPF10K10LC84-3 20 21 0 0 0 % 52 9 %User Pins: 20 21 0 Project Information c:\study\vhdl\codecs\g711.3\g711.rpt** PROJECT COMPILATION MESSAGES **Warning: Ignored unnecessary INPUT pin 'PCM_in0' Project Information c:\study\vhdl\codecs\g711.3\g711.rpt** FILE HIERARCHY **|shift:lpm_1||shift:lpm_1|lpm_clshift:lpm_clshift_component||lpm_clshift:lpm_2| Device-Specific Information: c:\study\vhdl\codecs\g711.3\g711.rptg711***** Logic for device 'g711' compiled without errors.Device: EPF10K10LC84-3FLEX 10K Configuration Scheme: Passive SerialDevice Options: User-Supplied Start-Up Clock = OFF Auto-Restart Configuration on Frame Error = OFF Release Clears Before Tri-States = OFF Enable Chip_Wide Reset = OFF Enable Chip-Wide Output Enable = OFF Enable INIT_DONE Output = OFF JTAG User Code = 7f ^ G G G C P P P 7 P 7 7 R G G R R R R R O C C C 1 C 1 1 E 7 P 7 E E E E E N M M M 1 M 1 1 V S 1 C 1 S G S S S S F _ _ _ _ _ _ _ C E 1 M 1 E N E E E E _ ^ o o o o o o o C R _ _ _ R D R R R R # D n u u u u u u u I V i i i V I V V V V T O C t t t t t t t N E n n n E N E E E E C N E 6 8 5 1 3 3 5 T D 6 6 5 D T D D D D K E O -----------------------------------------------------------------_ / 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 | ^DATA0 | 12 74 | #TDO ^DCLK | 13 73 | PCM_in9 ^nCE | 14 72 | PCM_in10 #TDI | 15 71 | PCM_in11 PCM_in3 | 16 70 | PCM_in5 PCM_in2 | 17 69 | PCM_in4 PCM_in1 | 18 68 | GNDINT G711_out6 | 19 67 | G711_in0 VCCINT | 20 66 | G711_in3 PCM_out4 | 21 65 | G711_in2 PCM_out0 | 22 EPF10K10LC84-3 64 | G711_in1 G711_out4 | 23 63 | VCCINT G711_out0 | 24 62 | G711_in7 PCM_out2 | 25 61 | PCM_in12 GNDINT | 26 60 | G711_out7 RESERVED | 27 59 | PCM_out10 PCM_out9 | 28 58 | PCM_out1 PCM_out12 | 29 57 | #TMS PCM_out7 | 30 56 | #TRST ^MSEL0 | 31 55 | ^nSTATUS ^MSEL1 | 32 54 | RESERVED |_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _| ------------------------------------------------------------------ V ^ G R P R R V G G P P V G R R R R R R R C n 7 E C E E C N 7 C C C N E E E E E E E C C 1 S M S S C D 1 M M C D S S S S S S S I O 1 E _ E E I I 1 _ _ I I E E E E E E E N N _ R o R R N N _ i i N N R R R R R R R T F o V u V V T T i n n T T V V V V V V V I u E t E E n 7 8 E E E E E E E G t D 1 D D 4 D D D D D D D 2 1 N.C. = No Connect. This pin has no internal connection to the device.VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.GNDIO = Dedicated ground pin, which MUST be connected to GND.RESERVED = Unused I/O pin, which MUST be left unconnected.^ = Dedicated configuration pin.+ = Reserved configuration pin, which is tri-stated during user mode.* = Reserved configuration pin, which drives out in user mode.PDn = Power Down pin. @ = Special-purpose pin. # = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions. Device-Specific Information: c:\study\vhdl\codecs\g711.3\g711.rptg711** RESOURCE USAGE **Logic Column Row Array Interconnect Interconnect Clears/ External Block Logic Cells Driven Driven Clocks Presets InterconnectA4 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 10/22( 45%) A5 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 10/22( 45%) A6 4/ 8( 50%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 9/22( 40%) A7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%) A8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%) A9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%) A10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%) A11 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/22( 27%) A12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%) B1 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 8/22( 36%) B2 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 8/22( 36%) B3 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 5/22( 22%) B8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%) B9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%) B12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%) C10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) C13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) Embedded Column Row Array Embedded Interconnect Interconnect Read/ External Block Cells Driven Driven Clocks Write InterconnectTotal dedicated input pins used: 6/6 (100%)Total I/O pins used: 35/53 ( 66%)Total logic cells used: 52/576 ( 9%)Total embedded cells used: 0/24 ( 0%)Total EABs used: 0/3 ( 0%)Average fan-in: 3.13/4 ( 78%)Total fan-in: 163/2304 ( 7%)Total input pins required: 20Total input I/O cell registers required: 0Total output pins required: 21Total output I/O cell registers required: 0Total buried I/O cell registers required: 0Total bidirectional pins required: 0Total reserved pins required 0Total logic cells required: 52Total flipflops required: 0Total packed registers required: 0Total logic cells in carry chains: 0Total number of carry chains: 0Total logic cells in cascade chains: 0Total number of cascade chains: 0Total single-pin Clock Enables required: 0Total single-pin Output Enables required: 0Synthesized logic cells: 3/ 576 ( 0%)Logic Cell and Embedded Cell CountsColumn: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC) A: 0 0 0 8 8 4 1 1 1 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 28/0 B: 8 8 3 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 22/0 C: 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 2/0 Total: 8 8 3 8 8 4 1 2 2 2 3 2 0 1 0 0 0 0 0 0 0 0 0 0 0 52/0 Device-Specific Information: c:\study\vhdl\codecs\g711.3\g711.rptg711** INPUTS ** Fan-In Fan-Out Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name 67 - - B -- INPUT 0 0 0 2 G711_in0 64 - - B -- INPUT 0 0 0 2 G711_in1 65 - - B -- INPUT 0 0 0 2 G711_in2 66 - - B -- INPUT 0 0 0 2 G711_in3 42 - - - -- INPUT 0 0 0 10 G711_in4 84 - - - -- INPUT 0 0 0 15 G711_in5 2 - - - -- INPUT 0 0 0 14 G711_in6 62 - - C -- INPUT 0 0 0 1 G711_in7 18 - - A -- INPUT 0 0 0 2 PCM_in1 17 - - A -- INPUT 0 0 0 2 PCM_in2 16 - - A -- INPUT 0 0 0 2 PCM_in3 69 - - A -- INPUT 0 0 0 2 PCM_in4 70 - - A -- INPUT 0 0 0 3 PCM_in5 1 - - - -- INPUT 0 0 0 5 PCM_in6 43 - - - -- INPUT 0 0 0 5 PCM_in7 44 - - - -- INPUT 0 0 0 5 PCM_in8 73 - - A -- INPUT 0 0 0 5 PCM_in9 72 - - A -- INPUT 0 0 0 4 PCM_in10 71 - - A -- INPUT 0 0 0 4 PCM_in11 61 - - C -- INPUT 0 0 0 1 PCM_in12Code:s = Synthesized pin or logic cell+ = Synchronous flipflop/ = Slow slew-rate output! = NOT gate push-backr = Fitter-inserted logic cell@ = Uses single-pin Clock Enable& = Uses single-pin Output Enable Device-Specific Information: c:\study\vhdl\codecs\g711.3\g711.rptg711** OUTPUTS ** Fed By Fed By Fan-In Fan-Out Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name 24 - - B -- OUTPUT 0 1 0 0 G711_out0 8 - - - 03 OUTPUT 0 1 0 0 G711_out1 35 - - - 06 OUTPUT 0 1 0 0 G711_out2 6 - - - 04 OUTPUT 0 1 0 0 G711_out3 23 - - B -- OUTPUT 0 1 0 0 G711_out4 5 - - - 05 OUTPUT 0 1 0 0 G711_out5 19 - - A -- OUTPUT 0 1 0 0 G711_out6 60 - - C -- OUTPUT 0 1 0 0 G711_out7 22 - - B -- OUTPUT 0 1 0 0 PCM_out0 58 - - C -- OUTPUT 0 1 0 0 PCM_out1 25 - - B -- OUTPUT 0 1 0 0 PCM_out2 7 - - - 03 OUTPUT 0 1 0 0 PCM_out3 21 - - B -- OUTPUT 0 1 0 0 PCM_out4 9 - - - 02 OUTPUT 0 1 0 0 PCM_out5 11 - - - 01 OUTPUT 0 1 0 0 PCM_out6 30 - - C -- OUTPUT 0 1 0 0 PCM_out7 10 - - - 01 OUTPUT 0 1 0 0 PCM_out8 28 - - C -- OUTPUT 0 1 0 0 PCM_out9 59 - - C -- OUTPUT 0 1 0 0 PCM_out10 37 - - - 09 OUTPUT 0 1 0 0 PCM_out11 29 - - C -- OUTPUT 0 1 0 0 PCM_out12Code:s = Synthesized pin or logic cell+ = Synchronous flipflop/ = Slow slew-rate output! = NOT gate push-backr = Fitter-inserted logic cell@ = Uses single-pin Clock Enable& = Uses single-pin Output Enable Device-Specific Information: c:\study\vhdl\codecs\g711.3\g711.rptg711** BURIED LOGIC ** Fan-In Fan-Out IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name - 4 - C 13 LCELL s 1 0 1 0 G711_out7~1 - 5 - B 01 OR2 4 0 0 2 |lpm_clshift:lpm_2|sbit1_0 - 8 - B 02 OR2 3 1 0 2 |lpm_clshift:lpm_2|sbit1_1 - 7 - B 01 OR2 3 1 0 3 |lpm_clshift:lpm_2|sbit1_2 - 5 - B 02 OR2 3 1 0 2 |lpm_clshift:lpm_2|sbit1_3 - 1 - B 12 OR2 4 0 0 4 |lpm_clshift:lpm_2|sbit1_4 - 4 - B 02 OR2 2 1 0 2 |lpm_clshift:lpm_2|sbit2_1 - 6 - B 01 OR2 1 2 0 2 |lpm_clshift:lpm_2|sbit2_2 - 2 - B 02 OR2 1 2 0 2 |lpm_clshift:lpm_2|sbit2_3 - 3 - B 01 OR2 1 2 0 1 |lpm_clshift:lpm_2|sbit2_4 - 7 - B 02 OR2 2 1 0 2 |lpm_clshift:lpm_2|sbit2_5 - 1 - B 03 OR2 3 1 1 0 |lpm_clshift:lpm_2|sbit3_3 - 1 - B 01 OR2 2 2 1 0 |lpm_clshift:lpm_2|sbit3_4 - 1 - B 02 OR2 1 2 1 0 |lpm_clshift:lpm_2|sbit3_5⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -