upsd3200.inc

DK3200开发板上的ADC开发出的AD和PWM应用程序

;--------------------------------------------------------------------------
;upsd3200.inc
;
;Version:
;September 10, 2004 Version 2.0 - Initial Version.
;
;Description:
;Header file for uPSD3200 microcontroller.
;
;Assembler: Ride
;
;Copyright (c) 2004 ST Microelectronics
;
;This example demo code is provided as is and has no warranty,
;implied or otherwise.  You are free to use/modify any of the provided
;code at your own risk in your applications with the expressed limitation
;of liability (see below) so long as your product using the code contains
;at least one uPSD product (device).
;
;LIMITATION OF LIABILITY:   NEITHER STMicroelectronics NOR ITS VENDORS OR 
;AGENTS SHALL BE LIABLE FOR ANY LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA,
;INTERRUPTION OF BUSINESS, NOR FOR INDIRECT, SPECIAL, INCIDENTAL OR
;CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER THIS AGREEMENT OR
;OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
;--------------------------------------------------------------------------

;  Standard Registers  	
$include (reg51.inc) ; Include standard 8051 Equates

;  8052 Extensions  	
T2CON   data 0C8H    ; // Timer 2 Control
T2MOD   data 0C9H    ; // Timer 2 Mode
RCAP2L  data 0CAH    ; // Timer 2 Reload low byte
RCAP2H  data 0CBH    ; // Timer 2 Reload high byte
TL2     data 0CCH    ; // Timer 2 low byte
TH2     data 0CDH    ; // Timer 2 high byte

;  uPSD Extensions 	
P4      data 0C0H    ; // Port 4
P1SFS   data 091H    ; // Port 1 I/O select
P3SFS   data 093H    ; // Port 3 I/O select
P4SFS   data 094H    ; // Port 4 I/O select

; ADC SFRs          
ASCL    data 095H    ; // ADC Clock Prescalar
ADAT    data 096H    ; // ADC Data Register
ACON    data 097H    ; // ADC Control Register

; DDC SFRs
S1SETUP data 0D1H    ; // DDC I2C (S1) Setup
RAMBUF  data 0D4H    ; // DDC RAM Buffer
DDCDAT  data 0D5H    ; // DDC Data Transmit Register
DDCADR  data 0D6H    ; // DDC Address Pointer Register
DDCCON  data 0D7H    ; // DDC Control Register 
S1CON   data 0D8H    ; // DDC I2C Control Register
S1STA   data 0D9H    ; // DDC I2C Status
S1DAT   data 0DAH    ; // DDC Data Hold Register
S1ADR   data 0DBH    ; // DDC I2C Address

; UART 1 SFRs        
SCON2   data 09AH    ; // UART 1 Serial Control
SBUF2   data 09BH    ; // UART 1 Serial Buffer

; PWM SFRs
PWMCON  data 0A1H    ; // PWM Polarity Control
PWM0    data 0A2H    ; // PWM0 Duty Cycle
PWM1    data 0A3H    ; // PWM1 Duty Cycle
PWM2    data 0A4H    ; // PWM2 Duty Cycle
PWM3    data 0A5H    ; // PWM3 Duty Cycle
PWM4P   data 0AAH    ; // PWM4 Period
PWM4W   data 0ABH    ; // PWM4 Pulse Width
PSCL0L  data 0B1H    ; // 8-bit PWM0 Prescaler low
PSCL0H  data 0B2H    ; // 8-bit PWM0 Prescaler high
PSCL1L  data 0B3H    ; // 8-bit PWM1 Prescaler low
PSCL1H  data 0B4H    ; // 8-bit PWM1 Prescaler high

;  WDT SFRs          
WDRST   data 0A6H    ; // Watch Dog Reset
WDKEY   data 0AEH    ; // Watch Dog Timer Enable

; INTERRUPT 2 SFRs  
IEA     data 0A7H    ; // Interrupt Enable (2nd)
IPA     data 0B7H    ; // Interrupt Priority (2nd)

; I2C SFRs
S2SETUP data 0D2H    ; // I2C (S2) Setup
S2CON   data 0DCH    ; // I2C Bus Control Register
S2STA   data 0DDH    ; // I2C Bus Status
S2DAT   data 0DEH    ; // I2C Data Hold Register
S2ADR   data 0DFH    ; // I2C Bus Address

; USB SFRs
USCL    data 0E1H    ; // USB Clock 8bit prescaler register
UDT1    data 0E6H    ; // USB End Point 1 Data Register
UDT0    data 0E7H    ; // USB End Point 0 Data register
UISTA   data 0E8H    ; // USB Interrupt Status
UIEN    data 0E9H    ; // USB Interrupt Enable
UCON0   data 0EAH    ; // USB End Point 0 Control
UCON1   data 0EBH    ; // USB End Point 1 Control
UCON2   data 0ECH    ; // USB End Point 2 Control
USTA    data 0EDH    ; // USB End Point 0 Status
UADR    data 0EEH    ; // USB Address Register
UDR0    data 0EFH    ; // USB Endpoint 0 Data Receive

; *****  BIT Registers  (the 8051 standard bits are included by reg51.inc)
;   IE  
ET2  BIT 0ADH     ; // Timer 2
             
;   T2CON  
TF2    BIT 0CFH   ;
EXF2   BIT 0CEH   ;
RCLK   BIT 0CDH   ;
TCLK   BIT 0CCH   ;
EXEN2  BIT 0CBH   ;
TR2    BIT 0CAH   ;
C_T2   BIT 0C9H   ;
CP_RL2 BIT 0C8H   ;

;    P4 GPIO   
P4_7 BIT 0C7H     ; // bit 7 of P4
P4_6 BIT 0C6H     ; // bit 6 of P4
P4_5 BIT 0C5H     ; // bit 5 of P4
P4_4 BIT 0C4H     ; // bit 4 of P4
P4_3 BIT 0C3H     ; // bit 3 of P4
P4_2 BIT 0C2H     ; // bit 2 of P4
P4_1 BIT 0C1H     ; // bit 1 of P4
P4_0 BIT 0C0H     ; // bit 0 of P4

;   S1CON   
SM01 BIT 0DFH     ;
SM11 BIT 0DEH     ;
SM21 BIT 0DDH     ;
REN1 BIT 0DCH     ;
TB81 BIT 0DBH     ;
RB81 BIT 0DAH     ;
TI1  BIT 0D9H     ;
RI1  BIT 0D8H     ;

;  S1CON
CR2  BIT 0DFH     ;
ENI1 BIT 0DEH     ;
STA  BIT 0DDH     ;
STO  BIT 0DCH     ;
ADDR BIT 0DBH     ;
AA   BIT 0DAH     ;
CR1  BIT 0D9H     ;
CR0  BIT 0D8H     ;

;  UISTA
SUSPND BIT 0EFH   ;
RSTF   BIT 0EDH   ;
TXD0F  BIT 0ECH   ;
RXD0F  BIT 0EBH   ;
RXD1F  BIT 0EAH   ;
EOPF   BIT 0E9H   ;
RESUMF BIT 0E8H   ;

;   IP  
PT2  BIT 0BDH     ; // Timer 2