vgacore.trt

VHDL-vga_core(vhdl).rar FPGA上实现 VGA的IP（VHDL）

============
Chip vgacore
============

Summary Information:
--------------------
Type: Initial implementation
Source: out-of-date
Status: 0 errors, 6 warnings, 1 messages

Target Information:
-------------------
Vendor: Xilinx
Family: XC4000
Device: 4005XLPC84
Speed: xl-3

Chip Parameters:
----------------
Optimize for: Speed
Optimization effort: Low
Frequency: 50 MHz
Is module: Yes
Keep io pads: No
Number of flip-flops: 0
Number of latches: 0

Chip Design Hierarchy:
----------------------
vgacore: defined in F:\XESSCORP\ELASCOMP\XSBRDS\designs\VGAVHDL\vgacore.vhd

Primitive reference count:
--------------------------

Clocks:
-------
                           Required  Estimated                       
Period   Rise     Fall     Freq      Freq       Signal               
(ns)     (ns)     (ns)     (MHz)     (MHz)                           
...............................................................
 20        0       10       50.00       n/a     default              
n/a      n/a      n/a         n/a    100.00     clock                
n/a      n/a      n/a         n/a    100.00     hsyncb               

Timing Groups:
--------------
                                                              
                                                              
Name                 Description                              
............................................................
(I)                  Input ports                              
(O)                  Output ports                             
(RC,clock)           Clocked by rising edge of clock          
(RC,hsyncb)          Clocked by rising edge of hsyncb         

Timing Path Groups:
-------------------
                                          Required   Estimated  
                                          Delay      Delay      
From                 To                   (ns)       (ns)       
............................................................
(I)                  (RC,clock)            20.00        n/a     
(I)                  (RC,hsyncb)           20.00        n/a     
(RC,clock)           (O)                   20.00        n/a     
(RC,clock)           (RC,clock)            20.00        n/a     
(RC,hsyncb)          (O)                   20.00        n/a     
(RC,hsyncb)          (RC,clock)            20.00        n/a     
(RC,hsyncb)          (RC,hsyncb)           20.00        n/a     

Input Port Timing:
------------------
                     Required   Estimated                       
Port                 Delay      Slack                           
Name                 (ns)       (ns)       To-Group             
............................................................
reset                 20.00        n/a     (RC,clock)           
clock                 20.00        n/a     (RC,clock)           
data<7>               20.00        n/a     (RC,clock)           
data<6>               20.00        n/a     (RC,clock)           
data<5>               20.00        n/a     (RC,clock)           
data<4>               20.00        n/a     (RC,clock)           
data<3>               20.00        n/a     (RC,clock)           
data<2>               20.00        n/a     (RC,clock)           
data<1>               20.00        n/a     (RC,clock)           
data<0>               20.00        n/a     (RC,clock)           

Output Port Timing:
-------------------
                     Required   Estimated                       
Port                 Delay      Slack                           
Name                 (ns)       (ns)       From-Group           
............................................................
hsyncb                20.00        n/a     (RC,clock)           
vsyncb                20.00        n/a     (RC,clock)           
rgb<5>                20.00        n/a     (RC,clock)           
rgb<4>                20.00        n/a     (RC,clock)           
rgb<3>                20.00        n/a     (RC,clock)           
rgb<2>                20.00        n/a     (RC,clock)           
rgb<1>                20.00        n/a     (RC,clock)           
rgb<0>                20.00        n/a     (RC,clock)           
addr<14>              20.00        n/a     (RC,clock)           
addr<13>              20.00        n/a     (RC,clock)           
addr<12>              20.00        n/a     (RC,clock)           
addr<11>              20.00        n/a     (RC,clock)           
addr<10>              20.00        n/a     (RC,clock)           
addr<9>               20.00        n/a     (RC,clock)           
addr<8>               20.00        n/a     (RC,clock)           
addr<7>               20.00        n/a     (RC,clock)           
addr<6>               20.00        n/a     (RC,clock)           
addr<5>               20.00        n/a     (RC,clock)           
addr<4>               20.00        n/a     (RC,clock)           
addr<3>               20.00        n/a     (RC,clock)           
addr<2>               20.00        n/a     (RC,clock)           
addr<1>               20.00        n/a     (RC,clock)           
addr<0>               20.00        n/a     (RC,clock)           
csb                   20.00        n/a     (RC,clock)           
oeb                   20.00        n/a     (RC,clock)           
web                   20.00        n/a     (RC,clock)