six_smg2.map.rpt

六个数码码动态扫描接口程序

+---------------------------------------------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |six_smg2                  ; 28 (28)     ; 14           ; 0           ; 15   ; 0            ; 14 (14)      ; 5 (5)             ; 9 (9)            ; 8 (8)           ; 0 (0)      ; |six_smg2           ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------+
; State Machine - |six_smg2|led1q ;
+---------------------------------+
; Name                            ;
+---------------------------------+
; led1q.1010                      ;
+---------------------------------+


+---------------------------------+
; State Machine - |six_smg2|led2q ;
+---------------------------------+
; Name                            ;
+---------------------------------+
; led2q.1011                      ;
+---------------------------------+


+---------------------------------+
; State Machine - |six_smg2|led3q ;
+---------------------------------+
; Name                            ;
+---------------------------------+
; led3q.1100                      ;
+---------------------------------+


+---------------------------------+
; State Machine - |six_smg2|led4q ;
+---------------------------------+
; Name                            ;
+---------------------------------+
; led4q.1101                      ;
+---------------------------------+


+---------------------------------+
; State Machine - |six_smg2|led5q ;
+---------------------------------+
; Name                            ;
+---------------------------------+
; led5q.1110                      ;
+---------------------------------+


+---------------------------------+
; State Machine - |six_smg2|led6q ;
+---------------------------------+
; Name                            ;
+---------------------------------+
; led6q.1111                      ;
+---------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 14    ;
; Number of registers using Synchronous Clear  ; 8     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 6     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/altera/verilogpro/ep1c6/six_smg2/six_smg2.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Fri Mar 23 12:45:34 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off six_smg2 -c six_smg2
Warning (10268): Verilog HDL information at six_smg2.v(60): Always Construct contains both blocking and non-blocking assignments
Info: Found 1 design units, including 1 entities, in source file six_smg2.v
    Info: Found entity 1: six_smg2
Info: Elaborating entity "six_smg2" for the top level hierarchy
Warning (10199): Verilog HDL Case Statement warning at six_smg2.v(38): case item expression is ignored because it never applies
Warning (10199): Verilog HDL Case Statement warning at six_smg2.v(39): case item expression is ignored because it never applies
Warning (10199): Verilog HDL Case Statement warning at six_smg2.v(40): case item expression is ignored because it never applies
Warning (10199): Verilog HDL Case Statement warning at six_smg2.v(41): case item expression is ignored because it never applies
Warning (10199): Verilog HDL Case Statement warning at six_smg2.v(42): case item expression is ignored because it never applies
Warning (10199): Verilog HDL Case Statement warning at six_smg2.v(43): case item expression is ignored because it never applies
Warning (10199): Verilog HDL Case Statement warning at six_smg2.v(44): case item expression is ignored because it never applies
Warning (10199): Verilog HDL Case Statement warning at six_smg2.v(45): case item expression is ignored because it never applies
Warning (10199): Verilog HDL Case Statement warning at six_smg2.v(46): case item expression is ignored because it never applies
Warning (10199): Verilog HDL Case Statement warning at six_smg2.v(47): case item expression is ignored because it never applies
Warning (10270): Verilog HDL statement warning at six_smg2.v(37): incomplete Case Statement has no default case item
Info (10264): Verilog HDL Case Statement information at six_smg2.v(37): all case item expressions in this case statement are onehot
Warning (10240): Verilog HDL Always Construct warning at six_smg2.v(19): variable "seg_out" may not be assigned a new value in every possible path through the Always Construct.  Variable "seg_out" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10230): Verilog HDL assignment warning at six_smg2.v(64): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at six_smg2.v(70): truncated value with size 32 to match size of target (6)
Warning: LATCH primitive "seg_out[0]" is permanently enabled
Warning: LATCH primitive "seg_out[1]" is permanently enabled
Warning: LATCH primitive "seg_out[2]" is permanently enabled
Warning: LATCH primitive "seg_out[3]" is permanently enabled
Warning: LATCH primitive "seg_out[5]" is permanently enabled
Warning: LATCH primitive "seg_out[6]" is permanently enabled
Info: State machine "|six_smg2|led1q" contains 1 states
Info: State machine "|six_smg2|led2q" contains 1 states
Info: State machine "|six_smg2|led3q" contains 1 states
Info: State machine "|six_smg2|led4q" contains 1 states
Info: State machine "|six_smg2|led5q" contains 1 states
Info: State machine "|six_smg2|led6q" contains 1 states
Info: Selected Auto state machine encoding method for state machine "|six_smg2|led1q"
Info: Encoding result for state machine "|six_smg2|led1q"
    Info: Completed encoding using 0 state bits
    Info: State "|six_smg2|led1q.1010" uses code string ""
Info: Selected Auto state machine encoding method for state machine "|six_smg2|led2q"
Info: Encoding result for state machine "|six_smg2|led2q"
    Info: Completed encoding using 0 state bits
    Info: State "|six_smg2|led2q.1011" uses code string ""
Info: Selected Auto state machine encoding method for state machine "|six_smg2|led3q"
Info: Encoding result for state machine "|six_smg2|led3q"
    Info: Completed encoding using 0 state bits
    Info: State "|six_smg2|led3q.1100" uses code string ""
Info: Selected Auto state machine encoding method for state machine "|six_smg2|led4q"
Info: Encoding result for state machine "|six_smg2|led4q"
    Info: Completed encoding using 0 state bits
    Info: State "|six_smg2|led4q.1101" uses code string ""
Info: Selected Auto state machine encoding method for state machine "|six_smg2|led5q"
Info: Encoding result for state machine "|six_smg2|led5q"
    Info: Completed encoding using 0 state bits
    Info: State "|six_smg2|led5q.1110" uses code string ""
Info: Selected Auto state machine encoding method for state machine "|six_smg2|led6q"
Info: Encoding result for state machine "|six_smg2|led6q"
    Info: Completed encoding using 0 state bits
    Info: State "|six_smg2|led6q.1111" uses code string ""
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "seg_e" stuck at VCC
    Warning: Pin "seg_h" stuck at GND
Info: Implemented 43 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 14 output pins
    Info: Implemented 28 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings
    Info: Processing ended: Fri Mar 23 12:45:39 2007
    Info: Elapsed time: 00:00:06