six_smg2.fit.eqn

六个数码码动态扫描接口程序

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--led_out[6] is led_out[6] at LC_X32_Y9_N6
--operation mode is normal

led_out[6]_lut_out = !led_out[3] # !led_out[4] # !A1L52;
led_out[6] = DFFEAS(led_out[6]_lut_out, GLOBAL(clk), VCC, , A1L4, , , , );


--A1L52 is rtl~23 at LC_X32_Y9_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

led_out[1]_qfbk = led_out[1];
A1L52 = led_out[2] & led_out[6] & led_out[1]_qfbk & led_out[5];

--led_out[1] is led_out[1] at LC_X32_Y9_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

led_out[1] = DFFEAS(A1L52, GLOBAL(clk), VCC, , A1L4, led_out[2], , , VCC);


--A1L1 is Decoder~272 at LC_X32_Y9_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

led_out[3]_qfbk = led_out[3];
A1L1 = led_out[4] & !led_out[3]_qfbk & A1L52;

--led_out[3] is led_out[3] at LC_X32_Y9_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

led_out[3] = DFFEAS(A1L1, GLOBAL(clk), VCC, , A1L4, led_out[4], , , VCC);


--A1L5 is Select~443 at LC_X32_Y9_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

led_out[2]_qfbk = led_out[2];
A1L5 = led_out[5] & (led_out[4] & (led_out[2]_qfbk $ led_out[3]) # !led_out[4] & led_out[2]_qfbk & led_out[3]);

--led_out[2] is led_out[2] at LC_X32_Y9_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

led_out[2] = DFFEAS(A1L5, GLOBAL(clk), VCC, , A1L4, led_out[3], , , VCC);


--A1L6 is Select~444 at LC_X32_Y9_N9
--operation mode is normal

A1L6 = A1L1 # !led_out[6] # !A1L5 # !led_out[1];


--A1L7 is Select~445 at LC_X32_Y9_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

led_out[4]_qfbk = led_out[4];
A1L7 = led_out[5] & led_out[6] & (led_out[4]_qfbk $ led_out[1]);

--led_out[4] is led_out[4] at LC_X32_Y9_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

led_out[4] = DFFEAS(A1L7, GLOBAL(clk), VCC, , A1L4, led_out[5], , , VCC);


--A1L8 is Select~446 at LC_X34_Y9_N9
--operation mode is normal

A1L8 = led_out[3] & A1L7 & (led_out[2]);


--A1L9 is Select~447 at LC_X32_Y9_N1
--operation mode is normal

A1L9 = led_out[6] & (led_out[4] & (led_out[2] $ led_out[1]) # !led_out[4] & led_out[2] & led_out[1]);


--A1L10 is Select~448 at LC_X32_Y9_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

led_out[5]_qfbk = led_out[5];
A1L10 = led_out[3] & led_out[5]_qfbk & A1L9;

--led_out[5] is led_out[5] at LC_X32_Y9_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

led_out[5] = DFFEAS(A1L10, GLOBAL(clk), VCC, , A1L4, led_out[6], , , VCC);


--A1L50 is reduce_or~107 at LC_X32_Y9_N7
--operation mode is normal

A1L50 = led_out[4] & (led_out[5] & (led_out[2] $ led_out[3]) # !led_out[5] & led_out[2] & led_out[3]) # !led_out[4] & led_out[5] & led_out[2] & led_out[3];


--A1L51 is reduce_or~108 at LC_X33_Y9_N2
--operation mode is normal

A1L51 = led_out[1] & (led_out[6] & A1L50);


--A1L11 is Select~449 at LC_X32_Y9_N5
--operation mode is normal

A1L11 = A1L52 & (!led_out[4] & led_out[3]);


--delay[6] is delay[6] at LC_X27_Y10_N6
--operation mode is arithmetic

delay[6]_carry_eqn = (!A1L27 & A1L31) # (A1L27 & A1L32);
delay[6]_lut_out = delay[6] $ (!delay[6]_carry_eqn);
delay[6] = DFFEAS(delay[6]_lut_out, GLOBAL(clk), VCC, , , , , A1L4, );

--A1L34 is delay[6]~111 at LC_X27_Y10_N6
--operation mode is arithmetic

A1L34_cout_0 = delay[6] & (!A1L31);
A1L34 = CARRY(A1L34_cout_0);

--A1L35 is delay[6]~111COUT1_147 at LC_X27_Y10_N6
--operation mode is arithmetic

A1L35_cout_1 = delay[6] & (!A1L32);
A1L35 = CARRY(A1L35_cout_1);


--delay[7] is delay[7] at LC_X27_Y10_N7
--operation mode is normal

delay[7]_carry_eqn = (!A1L27 & A1L34) # (A1L27 & A1L35);
delay[7]_lut_out = delay[7] $ (delay[7]_carry_eqn);
delay[7] = DFFEAS(delay[7]_lut_out, GLOBAL(clk), VCC, , , , , A1L4, );


--delay[3] is delay[3] at LC_X27_Y10_N3
--operation mode is arithmetic

delay[3]_lut_out = delay[3] $ A1L21;
delay[3] = DFFEAS(delay[3]_lut_out, GLOBAL(clk), VCC, , , , , A1L4, );

--A1L24 is delay[3]~119 at LC_X27_Y10_N3
--operation mode is arithmetic

A1L24_cout_0 = !A1L21 # !delay[3];
A1L24 = CARRY(A1L24_cout_0);

--A1L25 is delay[3]~119COUT1 at LC_X27_Y10_N3
--operation mode is arithmetic

A1L25_cout_1 = !A1L22 # !delay[3];
A1L25 = CARRY(A1L25_cout_1);


--delay[1] is delay[1] at LC_X27_Y10_N1
--operation mode is arithmetic

delay[1]_lut_out = delay[1] $ (A1L15);
delay[1] = DFFEAS(delay[1]_lut_out, GLOBAL(clk), VCC, , , , , A1L4, );

--A1L18 is delay[1]~123 at LC_X27_Y10_N1
--operation mode is arithmetic

A1L18_cout_0 = !A1L15 # !delay[1];
A1L18 = CARRY(A1L18_cout_0);

--A1L19 is delay[1]~123COUT1_144 at LC_X27_Y10_N1
--operation mode is arithmetic

A1L19_cout_1 = !A1L16 # !delay[1];
A1L19 = CARRY(A1L19_cout_1);


--delay[0] is delay[0] at LC_X27_Y10_N0
--operation mode is arithmetic

delay[0]_lut_out = !delay[0];
delay[0] = DFFEAS(delay[0]_lut_out, GLOBAL(clk), VCC, , , , , A1L4, );

--A1L15 is delay[0]~127 at LC_X27_Y10_N0
--operation mode is arithmetic

A1L15_cout_0 = delay[0];
A1L15 = CARRY(A1L15_cout_0);

--A1L16 is delay[0]~127COUT1_143 at LC_X27_Y10_N0
--operation mode is arithmetic

A1L16_cout_1 = delay[0];
A1L16 = CARRY(A1L16_cout_1);


--delay[2] is delay[2] at LC_X27_Y10_N2
--operation mode is arithmetic

delay[2]_lut_out = delay[2] $ (!A1L18);
delay[2] = DFFEAS(delay[2]_lut_out, GLOBAL(clk), VCC, , , , , A1L4, );

--A1L21 is delay[2]~131 at LC_X27_Y10_N2
--operation mode is arithmetic

A1L21_cout_0 = delay[2] & (!A1L18);
A1L21 = CARRY(A1L21_cout_0);

--A1L22 is delay[2]~131COUT1_145 at LC_X27_Y10_N2
--operation mode is arithmetic

A1L22_cout_1 = delay[2] & (!A1L19);
A1L22 = CARRY(A1L22_cout_1);


--A1L2 is LessThan~151 at LC_X27_Y10_N9
--operation mode is normal

A1L2 = delay[3] & (delay[1] # delay[0] # delay[2]);


--delay[4] is delay[4] at LC_X27_Y10_N4
--operation mode is arithmetic

delay[4]_lut_out = delay[4] $ !A1L24;
delay[4] = DFFEAS(delay[4]_lut_out, GLOBAL(clk), VCC, , , , , A1L4, );

--A1L27 is delay[4]~135 at LC_X27_Y10_N4
--operation mode is arithmetic

A1L27 = A1L28;


--delay[5] is delay[5] at LC_X27_Y10_N5
--operation mode is arithmetic

delay[5]_carry_eqn = (!A1L27 & GND) # (A1L27 & VCC);
delay[5]_lut_out = delay[5] $ delay[5]_carry_eqn;
delay[5] = DFFEAS(delay[5]_lut_out, GLOBAL(clk), VCC, , , , , A1L4, );

--A1L31 is delay[5]~139 at LC_X27_Y10_N5
--operation mode is arithmetic

A1L31_cout_0 = !A1L27 # !delay[5];
A1L31 = CARRY(A1L31_cout_0);

--A1L32 is delay[5]~139COUT1_146 at LC_X27_Y10_N5
--operation mode is arithmetic

A1L32_cout_1 = !A1L27 # !delay[5];
A1L32 = CARRY(A1L32_cout_1);


--A1L3 is LessThan~152 at LC_X26_Y10_N2
--operation mode is normal

A1L3 = delay[5] # delay[4];


--A1L4 is LessThan~153 at LC_X27_Y10_N8
--operation mode is normal

A1L4 = delay[7] & delay[6] & (A1L3 # A1L2);


--clk is clk at PIN_28
--operation mode is input

clk = INPUT();


--led1 is led1 at PIN_144
--operation mode is output

led1 = OUTPUT(led_out[1]);


--led2 is led2 at PIN_143
--operation mode is output

led2 = OUTPUT(led_out[2]);


--led3 is led3 at PIN_141
--operation mode is output

led3 = OUTPUT(led_out[3]);


--led4 is led4 at PIN_140
--operation mode is output

led4 = OUTPUT(led_out[4]);


--led5 is led5 at PIN_139
--operation mode is output

led5 = OUTPUT(led_out[5]);


--led6 is led6 at PIN_138
--operation mode is output

led6 = OUTPUT(led_out[6]);


--seg_a is seg_a at PIN_170
--operation mode is output

seg_a = OUTPUT(A1L6);


--seg_b is seg_b at PIN_168
--operation mode is output

seg_b = OUTPUT(A1L8);


--seg_c is seg_c at PIN_166
--operation mode is output

seg_c = OUTPUT(A1L10);


--seg_d is seg_d at PIN_164
--operation mode is output

seg_d = OUTPUT(A1L51);


--seg_e is seg_e at PIN_162
--operation mode is output

seg_e = OUTPUT(VCC);


--seg_f is seg_f at PIN_160
--operation mode is output

seg_f = OUTPUT(!A1L11);


--seg_g is seg_g at PIN_158
--operation mode is output

seg_g = OUTPUT(!A1L1);


--seg_h is seg_h at PIN_156
--operation mode is output

seg_h = OUTPUT(GND);