six_smg2.tan.rpt

六个数码码动态扫描接口程序

+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------+
; tco                                                                 ;
+-------+--------------+------------+------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To    ; From Clock ;
+-------+--------------+------------+------------+-------+------------+
; N/A   ; None         ; 12.133 ns  ; led_out[2] ; seg_a ; clk        ;
; N/A   ; None         ; 11.675 ns  ; led_out[5] ; seg_a ; clk        ;
; N/A   ; None         ; 11.631 ns  ; led_out[6] ; seg_a ; clk        ;
; N/A   ; None         ; 10.927 ns  ; led_out[2] ; seg_f ; clk        ;
; N/A   ; None         ; 10.763 ns  ; led_out[1] ; seg_a ; clk        ;
; N/A   ; None         ; 10.469 ns  ; led_out[5] ; seg_f ; clk        ;
; N/A   ; None         ; 10.425 ns  ; led_out[6] ; seg_f ; clk        ;
; N/A   ; None         ; 10.242 ns  ; led_out[4] ; seg_a ; clk        ;
; N/A   ; None         ; 10.194 ns  ; led_out[5] ; seg_d ; clk        ;
; N/A   ; None         ; 10.004 ns  ; led_out[2] ; seg_g ; clk        ;
; N/A   ; None         ; 9.955 ns   ; led_out[4] ; seg_d ; clk        ;
; N/A   ; None         ; 9.887 ns   ; led_out[6] ; seg_b ; clk        ;
; N/A   ; None         ; 9.787 ns   ; led_out[5] ; seg_b ; clk        ;
; N/A   ; None         ; 9.596 ns   ; led_out[3] ; seg_a ; clk        ;
; N/A   ; None         ; 9.557 ns   ; led_out[1] ; seg_f ; clk        ;
; N/A   ; None         ; 9.546 ns   ; led_out[5] ; seg_g ; clk        ;
; N/A   ; None         ; 9.502 ns   ; led_out[6] ; seg_g ; clk        ;
; N/A   ; None         ; 9.468 ns   ; led_out[2] ; seg_d ; clk        ;
; N/A   ; None         ; 9.335 ns   ; led_out[1] ; seg_b ; clk        ;
; N/A   ; None         ; 9.313 ns   ; led_out[3] ; seg_d ; clk        ;
; N/A   ; None         ; 9.023 ns   ; led_out[4] ; seg_b ; clk        ;
; N/A   ; None         ; 8.903 ns   ; led_out[6] ; seg_c ; clk        ;
; N/A   ; None         ; 8.892 ns   ; led_out[3] ; seg_b ; clk        ;
; N/A   ; None         ; 8.882 ns   ; led_out[6] ; seg_d ; clk        ;
; N/A   ; None         ; 8.783 ns   ; led_out[4] ; seg_c ; clk        ;
; N/A   ; None         ; 8.772 ns   ; led_out[1] ; seg_d ; clk        ;
; N/A   ; None         ; 8.649 ns   ; led_out[2] ; seg_c ; clk        ;
; N/A   ; None         ; 8.634 ns   ; led_out[1] ; seg_g ; clk        ;
; N/A   ; None         ; 8.494 ns   ; led_out[3] ; seg_c ; clk        ;
; N/A   ; None         ; 8.455 ns   ; led_out[1] ; seg_c ; clk        ;
; N/A   ; None         ; 8.417 ns   ; led_out[2] ; seg_b ; clk        ;
; N/A   ; None         ; 8.348 ns   ; led_out[4] ; seg_f ; clk        ;
; N/A   ; None         ; 8.187 ns   ; led_out[3] ; seg_f ; clk        ;
; N/A   ; None         ; 8.047 ns   ; led_out[4] ; seg_g ; clk        ;
; N/A   ; None         ; 7.848 ns   ; led_out[5] ; seg_c ; clk        ;
; N/A   ; None         ; 7.407 ns   ; led_out[3] ; seg_g ; clk        ;
; N/A   ; None         ; 7.149 ns   ; led_out[3] ; led3  ; clk        ;
; N/A   ; None         ; 7.143 ns   ; led_out[4] ; led4  ; clk        ;
; N/A   ; None         ; 7.134 ns   ; led_out[6] ; led6  ; clk        ;
; N/A   ; None         ; 7.119 ns   ; led_out[5] ; led5  ; clk        ;
; N/A   ; None         ; 6.708 ns   ; led_out[2] ; led2  ; clk        ;
; N/A   ; None         ; 6.691 ns   ; led_out[1] ; led1  ; clk        ;
+-------+--------------+------------+------------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Fri Mar 23 12:46:13 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off six_smg2 -c six_smg2 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 192.94 MHz between source register "delay[5]" and destination register "led_out[1]" (period= 5.183 ns)
    Info: + Longest register to register delay is 4.890 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y10_N5; Fanout = 4; REG Node = 'delay[5]'
        Info: 2: + IC(0.765 ns) + CELL(0.292 ns) = 1.057 ns; Loc. = LC_X26_Y10_N2; Fanout = 1; COMB Node = 'LessThan~152'
        Info: 3: + IC(0.666 ns) + CELL(0.442 ns) = 2.165 ns; Loc. = LC_X27_Y10_N8; Fanout = 14; COMB Node = 'LessThan~153'
        Info: 4: + IC(1.858 ns) + CELL(0.867 ns) = 4.890 ns; Loc. = LC_X32_Y9_N3; Fanout = 6; REG Node = 'led_out[1]'
        Info: Total cell delay = 1.601 ns ( 32.74 % )
        Info: Total interconnect delay = 3.289 ns ( 67.26 % )
    Info: - Smallest clock skew is -0.032 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.910 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 14; CLK Node = 'clk'
            Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X32_Y9_N3; Fanout = 6; REG Node = 'led_out[1]'
            Info: Total cell delay = 2.180 ns ( 74.91 % )
            Info: Total interconnect delay = 0.730 ns ( 25.09 % )
        Info: - Longest clock path from clock "clk" to source register is 2.942 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 14; CLK Node = 'clk'
            Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X27_Y10_N5; Fanout = 4; REG Node = 'delay[5]'
            Info: Total cell delay = 2.180 ns ( 74.10 % )
            Info: Total interconnect delay = 0.762 ns ( 25.90 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "seg_a" through register "led_out[2]" is 12.133 ns
    Info: + Longest clock path from clock "clk" to source register is 2.910 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X32_Y9_N4; Fanout = 7; REG Node = 'led_out[2]'
        Info: Total cell delay = 2.180 ns ( 74.91 % )
        Info: Total interconnect delay = 0.730 ns ( 25.09 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 8.999 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X32_Y9_N4; Fanout = 7; REG Node = 'led_out[2]'
        Info: 2: + IC(1.158 ns) + CELL(0.590 ns) = 1.748 ns; Loc. = LC_X32_Y9_N3; Fanout = 3; COMB Node = 'rtl~23'
        Info: 3: + IC(1.113 ns) + CELL(0.114 ns) = 2.975 ns; Loc. = LC_X32_Y9_N0; Fanout = 2; COMB Node = 'Decoder~272'
        Info: 4: + IC(1.095 ns) + CELL(0.590 ns) = 4.660 ns; Loc. = LC_X32_Y9_N9; Fanout = 1; COMB Node = 'Select~444'
        Info: 5: + IC(2.215 ns) + CELL(2.124 ns) = 8.999 ns; Loc. = PIN_170; Fanout = 0; PIN Node = 'seg_a'
        Info: Total cell delay = 3.418 ns ( 37.98 % )
        Info: Total interconnect delay = 5.581 ns ( 62.02 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Mar 23 12:46:14 2007
    Info: Elapsed time: 00:00:02