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📄 key1.map.rpt

📁 一个4*4矩阵键盘的VERILOG接口程序设计(FPGA)
💻 RPT
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Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |key1|scan_key                                                                                                                                                                                                                                                ;
+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+
; Name          ; scan_key.1111 ; scan_key.0001 ; scan_key.0010 ; scan_key.0011 ; scan_key.0100 ; scan_key.0101 ; scan_key.0110 ; scan_key.0111 ; scan_key.1000 ; scan_key.1001 ; scan_key.1010 ; scan_key.1011 ; scan_key.1100 ; scan_key.1101 ; scan_key.1110 ; scan_key.0000 ;
+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+
; scan_key.0000 ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ;
; scan_key.1110 ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ; 1             ;
; scan_key.1101 ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ; 0             ; 1             ;
; scan_key.1100 ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ; 0             ; 0             ; 1             ;
; scan_key.1011 ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ; 0             ; 0             ; 0             ; 1             ;
; scan_key.1010 ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ; 0             ; 0             ; 0             ; 0             ; 1             ;
; scan_key.1001 ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ;
; scan_key.1000 ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ;
; scan_key.0111 ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ;
; scan_key.0110 ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ;
; scan_key.0101 ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ;
; scan_key.0100 ; 0             ; 0             ; 0             ; 0             ; 1             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ;
; scan_key.0011 ; 0             ; 0             ; 0             ; 1             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ;
; scan_key.0010 ; 0             ; 0             ; 1             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ;
; scan_key.0001 ; 0             ; 1             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ;
; scan_key.1111 ; 1             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ; 1             ;
+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 35    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 35    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 19    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; row[1]~reg0                            ; 11      ;
; row[2]~reg0                            ; 11      ;
; row[3]~reg0                            ; 12      ;
; Total number of inverted registers = 3 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 30:1               ; 4 bits    ; 80 LEs        ; 24 LEs               ; 56 LEs                 ; No         ; |key1|Select~17            ;
; 30:1               ; 4 bits    ; 80 LEs        ; 24 LEs               ; 56 LEs                 ; No         ; |key1|Select~31            ;
; 30:1               ; 4 bits    ; 80 LEs        ; 24 LEs               ; 56 LEs                 ; No         ; |key1|Select~24            ;
; 30:1               ; 4 bits    ; 80 LEs        ; 24 LEs               ; 56 LEs                 ; No         ; |key1|Select~20            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Feb 18 13:28:54 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off key1 -c key1
Info: Found 1 design units, including 1 entities, in source file key1.v
    Info: Found entity 1: key1
Info: Elaborating entity "key1" for the top level hierarchy
Warning: Verilog HDL assignment warning at key1.v(24): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at key1.v(27): truncated value with size 32 to match size of target (16)
Warning: (10270) Verilog HDL statement warning at key1.v(44): incomplete Case Statement has no default case item
Warning: (10270) Verilog HDL statement warning at key1.v(59): incomplete Case Statement has no default case item
Warning: (10270) Verilog HDL statement warning at key1.v(74): incomplete Case Statement has no default case item
Warning: (10270) Verilog HDL statement warning at key1.v(89): incomplete Case Statement has no default case item
Info: State machine "|key1|scan_key" contains 16 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|key1|scan_key"
Info: Encoding result for state machine "|key1|scan_key"
    Info: Completed encoding using 16 state bits
        Info: Encoded state bit "scan_key.1111"
        Info: Encoded state bit "scan_key.0001"
        Info: Encoded state bit "scan_key.0010"
        Info: Encoded state bit "scan_key.0011"
        Info: Encoded state bit "scan_key.0100"
        Info: Encoded state bit "scan_key.0101"
        Info: Encoded state bit "scan_key.0110"
        Info: Encoded state bit "scan_key.0111"
        Info: Encoded state bit "scan_key.1000"
        Info: Encoded state bit "scan_key.1001"
        Info: Encoded state bit "scan_key.1010"
        Info: Encoded state bit "scan_key.1011"
        Info: Encoded state bit "scan_key.1100"
        Info: Encoded state bit "scan_key.1101"
        Info: Encoded state bit "scan_key.1110"
        Info: Encoded state bit "scan_key.0000"
    Info: State "|key1|scan_key.0000" uses code string "0000000000000000"
    Info: State "|key1|scan_key.1110" uses code string "0000000000000011"
    Info: State "|key1|scan_key.1101" uses code string "0000000000000101"
    Info: State "|key1|scan_key.1100" uses code string "0000000000001001"
    Info: State "|key1|scan_key.1011" uses code string "0000000000010001"
    Info: State "|key1|scan_key.1010" uses code string "0000000000100001"
    Info: State "|key1|scan_key.1001" uses code string "0000000001000001"
    Info: State "|key1|scan_key.1000" uses code string "0000000010000001"
    Info: State "|key1|scan_key.0111" uses code string "0000000100000001"
    Info: State "|key1|scan_key.0110" uses code string "0000001000000001"
    Info: State "|key1|scan_key.0101" uses code string "0000010000000001"
    Info: State "|key1|scan_key.0100" uses code string "0000100000000001"
    Info: State "|key1|scan_key.0011" uses code string "0001000000000001"
    Info: State "|key1|scan_key.0010" uses code string "0010000000000001"
    Info: State "|key1|scan_key.0001" uses code string "0100000000000001"
    Info: State "|key1|scan_key.1111" uses code string "1000000000000001"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "dataout[0]" stuck at VCC
    Warning: Pin "en[0]" stuck at GND
    Warning: Pin "en[1]" stuck at VCC
    Warning: Pin "en[2]" stuck at VCC
    Warning: Pin "en[3]" stuck at VCC
    Warning: Pin "en[4]" stuck at VCC
    Warning: Pin "en[5]" stuck at VCC
    Warning: Pin "en[6]" stuck at VCC
    Warning: Pin "en[7]" stuck at VCC
Info: Registers with preset signals will power-up high
Info: Implemented 92 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 20 output pins
    Info: Implemented 66 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings
    Info: Processing ended: Sat Feb 18 13:28:58 2006
    Info: Elapsed time: 00:00:04


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