key1.tan.qmsg

一个4*4矩阵键盘的VERILOG接口程序设计（FPGA）

{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[4\] scan_key.0111 14.705 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[4\]\" through register \"scan_key.0111\" is 14.705 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.720 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 35 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 35; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "" { clk } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns scan_key.0111 2 REG LC_X15_Y9_N6 3 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X15_Y9_N6; Fanout = 3; REG Node = 'scan_key.0111'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "5.588 ns" { clk scan_key.0111 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "6.720 ns" { clk scan_key.0111 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout scan_key.0111 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.609 ns + Longest register pin " "Info: + Longest register to pin delay is 7.609 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scan_key.0111 1 REG LC_X15_Y9_N6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y9_N6; Fanout = 3; REG Node = 'scan_key.0111'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "" { scan_key.0111 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.936 ns) + CELL(0.914 ns) 1.850 ns reduce_or~144 2 COMB LC_X15_Y9_N2 2 " "Info: 2: + IC(0.936 ns) + CELL(0.914 ns) = 1.850 ns; Loc. = LC_X15_Y9_N2; Fanout = 2; COMB Node = 'reduce_or~144'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "1.850 ns" { scan_key.0111 reduce_or~144 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.182 ns) + CELL(0.511 ns) 3.543 ns reduce_or~10 3 COMB LC_X14_Y9_N0 1 " "Info: 3: + IC(1.182 ns) + CELL(0.511 ns) = 3.543 ns; Loc. = LC_X14_Y9_N0; Fanout = 1; COMB Node = 'reduce_or~10'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "1.693 ns" { reduce_or~144 reduce_or~10 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.744 ns) + CELL(2.322 ns) 7.609 ns dataout\[4\] 4 PIN PIN_113 0 " "Info: 4: + IC(1.744 ns) + CELL(2.322 ns) = 7.609 ns; Loc. = PIN_113; Fanout = 0; PIN Node = 'dataout\[4\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "4.066 ns" { reduce_or~10 dataout[4] } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.747 ns 49.24 % " "Info: Total cell delay = 3.747 ns ( 49.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.862 ns 50.76 % " "Info: Total interconnect delay = 3.862 ns ( 50.76 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "7.609 ns" { scan_key.0111 reduce_or~144 reduce_or~10 dataout[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.609 ns" { scan_key.0111 reduce_or~144 reduce_or~10 dataout[4] } { 0.000ns 0.936ns 1.182ns 1.744ns } { 0.000ns 0.914ns 0.511ns 2.322ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "6.720 ns" { clk scan_key.0111 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout scan_key.0111 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "7.609 ns" { scan_key.0111 reduce_or~144 reduce_or~10 dataout[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.609 ns" { scan_key.0111 reduce_or~144 reduce_or~10 dataout[4] } { 0.000ns 0.936ns 1.182ns 1.744ns } { 0.000ns 0.914ns 0.511ns 2.322ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "scan_key.0010 column\[2\] clk 2.849 ns register " "Info: th for register \"scan_key.0010\" (data pin = \"column\[2\]\", clock pin = \"clk\") is 2.849 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.720 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 35 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 35; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "" { clk } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns scan_key.0010 2 REG LC_X16_Y9_N1 2 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X16_Y9_N1; Fanout = 2; REG Node = 'scan_key.0010'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "5.588 ns" { clk scan_key.0010 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "6.720 ns" { clk scan_key.0010 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout scan_key.0010 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.092 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.092 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns column\[2\] 1 PIN PIN_98 10 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_98; Fanout = 10; PIN Node = 'column\[2\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "" { column[2] } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.156 ns) + CELL(0.804 ns) 4.092 ns scan_key.0010 2 REG LC_X16_Y9_N1 2 " "Info: 2: + IC(2.156 ns) + CELL(0.804 ns) = 4.092 ns; Loc. = LC_X16_Y9_N1; Fanout = 2; REG Node = 'scan_key.0010'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "2.960 ns" { column[2] scan_key.0010 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.936 ns 47.31 % " "Info: Total cell delay = 1.936 ns ( 47.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.156 ns 52.69 % " "Info: Total interconnect delay = 2.156 ns ( 52.69 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "4.092 ns" { column[2] scan_key.0010 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.092 ns" { column[2] column[2]~combout scan_key.0010 } { 0.000ns 0.000ns 2.156ns } { 0.000ns 1.132ns 0.804ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "6.720 ns" { clk scan_key.0010 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout scan_key.0010 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "4.092 ns" { column[2] scan_key.0010 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.092 ns" { column[2] column[2]~combout scan_key.0010 } { 0.000ns 0.000ns 2.156ns } { 0.000ns 1.132ns 0.804ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 13:29:13 2006 " "Info: Processing ended: Sat Feb 18 13:29:13 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}