📄 key1.tan.qmsg
字号:
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 7 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register row\[3\]~reg0 register scan_key.0011 121.52 MHz 8.229 ns Internal " "Info: Clock \"clk\" has Internal fmax of 121.52 MHz between source register \"row\[3\]~reg0\" and destination register \"scan_key.0011\" (period= 8.229 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.520 ns + Longest register register " "Info: + Longest register to register delay is 7.520 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns row\[3\]~reg0 1 REG LC_X14_Y9_N1 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y9_N1; Fanout = 12; REG Node = 'row\[3\]~reg0'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "" { row[3]~reg0 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.334 ns) + CELL(0.740 ns) 3.074 ns Select~2206 2 COMB LC_X15_Y6_N7 1 " "Info: 2: + IC(2.334 ns) + CELL(0.740 ns) = 3.074 ns; Loc. = LC_X15_Y6_N7; Fanout = 1; COMB Node = 'Select~2206'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "3.074 ns" { row[3]~reg0 Select~2206 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.765 ns) + CELL(0.511 ns) 4.350 ns Select~2207 3 COMB LC_X15_Y6_N6 4 " "Info: 3: + IC(0.765 ns) + CELL(0.511 ns) = 4.350 ns; Loc. = LC_X15_Y6_N6; Fanout = 4; COMB Node = 'Select~2207'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "1.276 ns" { Select~2206 Select~2207 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.927 ns) + CELL(1.243 ns) 7.520 ns scan_key.0011 4 REG LC_X16_Y9_N6 2 " "Info: 4: + IC(1.927 ns) + CELL(1.243 ns) = 7.520 ns; Loc. = LC_X16_Y9_N6; Fanout = 2; REG Node = 'scan_key.0011'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "3.170 ns" { Select~2207 scan_key.0011 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.494 ns 33.16 % " "Info: Total cell delay = 2.494 ns ( 33.16 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.026 ns 66.84 % " "Info: Total interconnect delay = 5.026 ns ( 66.84 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "7.520 ns" { row[3]~reg0 Select~2206 Select~2207 scan_key.0011 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.520 ns" { row[3]~reg0 Select~2206 Select~2207 scan_key.0011 } { 0.000ns 2.334ns 0.765ns 1.927ns } { 0.000ns 0.740ns 0.511ns 1.243ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.720 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 35 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 35; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "" { clk } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns scan_key.0011 2 REG LC_X16_Y9_N6 2 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X16_Y9_N6; Fanout = 2; REG Node = 'scan_key.0011'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "5.588 ns" { clk scan_key.0011 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "6.720 ns" { clk scan_key.0011 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout scan_key.0011 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.720 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 35 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 35; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "" { clk } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns row\[3\]~reg0 2 REG LC_X14_Y9_N1 12 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X14_Y9_N1; Fanout = 12; REG Node = 'row\[3\]~reg0'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "5.588 ns" { clk row[3]~reg0 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 22 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "6.720 ns" { clk row[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout row[3]~reg0 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "6.720 ns" { clk scan_key.0011 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout scan_key.0011 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "6.720 ns" { clk row[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout row[3]~reg0 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 22 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } } } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "7.520 ns" { row[3]~reg0 Select~2206 Select~2207 scan_key.0011 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.520 ns" { row[3]~reg0 Select~2206 Select~2207 scan_key.0011 } { 0.000ns 2.334ns 0.765ns 1.927ns } { 0.000ns 0.740ns 0.511ns 1.243ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "6.720 ns" { clk scan_key.0011 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout scan_key.0011 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "6.720 ns" { clk row[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout row[3]~reg0 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "scan_key.0001 column\[0\] clk 2.854 ns register " "Info: tsu for register \"scan_key.0001\" (data pin = \"column\[0\]\", clock pin = \"clk\") is 2.854 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.241 ns + Longest pin register " "Info: + Longest pin to register delay is 9.241 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns column\[0\] 1 PIN PIN_102 17 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_102; Fanout = 17; PIN Node = 'column\[0\]'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "" { column[0] } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.348 ns) + CELL(0.511 ns) 3.991 ns reduce_or~147 2 COMB LC_X16_Y6_N0 4 " "Info: 2: + IC(2.348 ns) + CELL(0.511 ns) = 3.991 ns; Loc. = LC_X16_Y6_N0; Fanout = 4; COMB Node = 'reduce_or~147'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "2.859 ns" { column[0] reduce_or~147 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.166 ns) + CELL(0.914 ns) 6.071 ns Select~2207 3 COMB LC_X15_Y6_N6 4 " "Info: 3: + IC(1.166 ns) + CELL(0.914 ns) = 6.071 ns; Loc. = LC_X15_Y6_N6; Fanout = 4; COMB Node = 'Select~2207'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "2.080 ns" { reduce_or~147 Select~2207 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.927 ns) + CELL(1.243 ns) 9.241 ns scan_key.0001 4 REG LC_X16_Y9_N5 4 " "Info: 4: + IC(1.927 ns) + CELL(1.243 ns) = 9.241 ns; Loc. = LC_X16_Y9_N5; Fanout = 4; REG Node = 'scan_key.0001'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "3.170 ns" { Select~2207 scan_key.0001 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 41.12 % " "Info: Total cell delay = 3.800 ns ( 41.12 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.441 ns 58.88 % " "Info: Total interconnect delay = 5.441 ns ( 58.88 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "9.241 ns" { column[0] reduce_or~147 Select~2207 scan_key.0001 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.241 ns" { column[0] column[0]~combout reduce_or~147 Select~2207 scan_key.0001 } { 0.000ns 0.000ns 2.348ns 1.166ns 1.927ns } { 0.000ns 1.132ns 0.511ns 0.914ns 1.243ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.720 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 35 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 35; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "" { clk } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns scan_key.0001 2 REG LC_X16_Y9_N5 4 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X16_Y9_N5; Fanout = 4; REG Node = 'scan_key.0001'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "5.588 ns" { clk scan_key.0001 } "NODE_NAME" } "" } } { "key1.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/key1.v" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "6.720 ns" { clk scan_key.0001 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout scan_key.0001 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "9.241 ns" { column[0] reduce_or~147 Select~2207 scan_key.0001 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.241 ns" { column[0] column[0]~combout reduce_or~147 Select~2207 scan_key.0001 } { 0.000ns 0.000ns 2.348ns 1.166ns 1.927ns } { 0.000ns 1.132ns 0.511ns 0.914ns 1.243ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1_cmp.qrpt" Compiler "key1" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/db/key1.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/接口实验/矩阵键盘/key1/" "" "6.720 ns" { clk scan_key.0001 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout scan_key.0001 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0}
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