baud.vhd

ISE7.1

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-- Company: 
-- Engineer:
--
-- Create Date:    23:43:54 09/20/06
-- Design Name:    
-- Module Name:    baud - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity baud is
    Port ( clk : in std_logic; ---晶振时钟
           resetb : in std_logic;  ---系统复位
          baud_bclk :out std_logic);------采样时钟
end baud;

architecture Behavioral of baud is

begin
	  process(clk,resetb)
	  variable cnt:integer:=0;
	  begin
		 if rising_edge(clk)then
		     if resetb='0' then 
			     cnt:=0;
				  baud_bclk<='0'; 
		     elsif cnt>=32 then 
			     cnt:=0;
				  baud_bclk<='1';	 ------20mhz分频到38400约521	除以采样频率16  约等于33
		     else 
				  cnt:=cnt+1;
				  baud_bclk<='0';
		     end if;
	    end if;
	 end	  process;

end Behavioral;