top_fmdm_project.par

ISE7.1

Release 7.1.04i par H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

BIT-35FA9961BCD::  Tue Jul 24 10:27:11 2007

par -w -intstyle ise -ol std -t 1 top_fmdm_project_map.ncd top_fmdm_project.ncd
top_fmdm_project.pcf 


Constraints file: top_fmdm_project.pcf.
Loading device for application Rf_Device from file '2v500.nph' in environment
D:/Xilinx.
   "top_fmdm_project" is an NCD, version 3.1, device xc2v500, package fg456,
speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.425 Volts. (default - Range: 1.425 to 1.575 Volts)

WARNING:Timing:2666 - Constraint ignored: PATH "TS_U_TO_D_path" TIG;

Device speed data version:  "PRODUCTION 1.121 2005-07-22".


Device Utilization Summary:

   Number of BSCANs                    1 out of 1     100%
   Number of BUFGMUXs                  4 out of 16     25%
   Number of External IOBs            74 out of 264    28%
      Number of LOCed IOBs            74 out of 74    100%

   Number of RAMB16s                  21 out of 32     65%
   Number of SLICEs                  771 out of 3072   25%


Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 3 secs 
Finished initial Timing Analysis.  REAL time: 3 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98d41d) REAL time: 3 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 3 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 4 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 4 secs 

Phase 7.8
...............
..
Phase 7.8 (Checksum:ad8e9f) REAL time: 9 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 9 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 10 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 10 secs 

Phase 11.27
Phase 11.27 (Checksum:68e7775) REAL time: 10 secs 

Phase 12.24
Phase 12.24 (Checksum:7270df4) REAL time: 10 secs 

Writing design to file top_fmdm_project.ncd


Total REAL time to Placer completion: 11 secs 
Total CPU time to Placer completion: 11 secs 

Starting Router

Phase 1: 6274 unrouted;       REAL time: 14 secs 

Phase 2: 5205 unrouted;       REAL time: 14 secs 

Phase 3: 1019 unrouted;       REAL time: 15 secs 

Phase 4: 1019 unrouted; (0)      REAL time: 15 secs 

Phase 5: 1019 unrouted; (0)      REAL time: 15 secs 

Phase 6: 1019 unrouted; (0)      REAL time: 15 secs 

Phase 7: 0 unrouted; (0)      REAL time: 16 secs 

Phase 8: 0 unrouted; (0)      REAL time: 17 secs 

WARNING:Route - CLK Net:adc1_clk_OBUF
may have excessive skew because 2 NON-CLK pins
failed to route using a CLK template.
WARNING:Route - CLK Net:data_adjust_log/mux_en
may have excessive skew because 4 NON-CLK pins
failed to route using a CLK template.

Total REAL time to Router completion: 17 secs 
Total CPU time to Router completion: 17 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|    icon_control0<0> |     BUFGMUX7P| No   |  105 |  0.244     |  1.034      |
+---------------------+--------------+------+------+------------+-------------+
|       adc1_clk_OBUF |     BUFGMUX4S| No   |  202 |  0.213     |  1.021      |
+---------------------+--------------+------+------+------------+-------------+
|      clk20mhz_BUFGP |     BUFGMUX2S| No   |   17 |  0.007     |  1.006      |
+---------------------+--------------+------+------+------------+-------------+
|uart/u_baud/baud_bcl |              |      |      |            |             |
|                   k |     BUFGMUX1P| No   |  288 |  0.232     |  1.022      |
+---------------------+--------------+------+------+------------+-------------+
|U_icon_pro/iupdate_o |              |      |      |            |             |
|                  ut |         Local|      |    1 |  0.000     |  1.349      |
+---------------------+--------------+------+------+------------+-------------+
|data_adjust_log/mux_ |              |      |      |            |             |
|                  en |         Local|      |   12 |  0.026     |  1.627      |
+---------------------+--------------+------+------+------------+-------------+


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.209
   The MAXIMUM PIN DELAY IS:                               7.269
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   6.012

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 8.00  d >= 8.00
   ---------   ---------   ---------   ---------   ---------   ---------
        3166        1462         579         397         150           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_J_TO_J = MAXDELAY FROM TIMEGRP "J_CLK" | 30.000ns   | 10.456ns   | 7    
   TO TIMEGRP "J_CLK" 30 ns                 |            |            |      
--------------------------------------------------------------------------------
  TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" | 15.000ns   | 2.683ns    | 1    
   TO TIMEGRP "J_CLK" 15 ns                 |            |            |      
--------------------------------------------------------------------------------
  TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" | 15.000ns   | 2.820ns    | 0    
   TO TIMEGRP "U_CLK" 15 ns                 |            |            |      
--------------------------------------------------------------------------------
  PATH "TS_U_TO_D_path" TIG                 | N/A        | N/A        | N/A  
--------------------------------------------------------------------------------
  PATH "TS_J_TO_D_path" TIG                 | N/A        | 5.501ns    | 0    
--------------------------------------------------------------------------------
  PATH "TS_D_TO_J_path" TIG                 | N/A        | 6.923ns    | 5    
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 19 secs 
Total CPU time to PAR completion: 19 secs 

Peak Memory Usage:  111 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 3
Number of info messages: 0

Writing design to file top_fmdm_project.ncd



PAR done!