narrow_wide_pulse_generate.syr

ISE7.1

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: narrow_wide_pulse_generate.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "narrow_wide_pulse_generate.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "narrow_wide_pulse_generate"
Output Format                      : NGC
Target Device                      : xc2v500-4-fg456

---- Source Options
Top Module Name                    : narrow_wide_pulse_generate
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : narrow_wide_pulse_generate.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" in Library work.
Entity <narrow_wide_pulse_generate> compiled.
Entity <narrow_wide_pulse_generate> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <narrow_wide_pulse_generate> (Architecture <behavioral>).
Entity <narrow_wide_pulse_generate> analyzed. Unit <narrow_wide_pulse_generate> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <narrow_wide_pulse_generate>.
    Related source file is "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd".
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | log                                            |
    | Power Up State     | log                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <narrow_wide_pulse>.
    Found 32-bit comparator greatequal for signal <$n0004> created at line 70.
    Found 32-bit comparator greater for signal <$n0005> created at line 79.
    Found 32-bit comparator greater for signal <$n0006> created at line 88.
    Found 32-bit adder for signal <$n0012> created at line 68.
    Found 32-bit register for signal <cnt>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  33 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   3 Comparator(s).
Unit <narrow_wide_pulse_generate> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:2]> with sequential encoding.
--------------------
 State  | Encoding
--------------------
 log    | 00
 narrow | 01
 wide   | 10
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 1
 32-bit adder                      : 1
# Registers                        : 4
 1-bit register                    : 3
 32-bit register                   : 1
# Comparators                      : 3
 32-bit comparator greatequal      : 1
 32-bit comparator greater         : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <narrow_wide_pulse_generate> ...
Loading device for application Rf_Device from file '2v500.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block narrow_wide_pulse_generate, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : narrow_wide_pulse_generate.ngr
Top Level Output File Name         : narrow_wide_pulse_generate
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 3

Macro Statistics :
# Registers                        : 2
#      1-bit register              : 1
#      32-bit register             : 1
# Adders/Subtractors               : 1
#      32-bit adder                : 1
# Comparators                      : 3
#      32-bit comparator greatequal: 1
#      32-bit comparator greater   : 2

Cell Usage :
# BELS                             : 219
#      GND                         : 1
#      INV                         : 7
#      LUT1_L                      : 33
#      LUT2_L                      : 2
#      LUT3_L                      : 2
#      LUT4_D                      : 2
#      LUT4_L                      : 67
#      MUXCY                       : 59
#      MUXF5                       : 14
#      VCC                         : 1
#      XORCY                       : 31
# FlipFlops/Latches                : 35
#      FDC                         : 34
#      FDP                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 2
#      IBUF                        : 1
#      OBUF                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v500fg456-4 

 Number of Slices:                      58  out of   3072     1%  
 Number of Slice Flip Flops:            35  out of   6144     0%  
 Number of 4 input LUTs:               106  out of   6144     1%  
 Number of bonded IOBs:                  3  out of    264     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 35    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.264ns (Maximum Frequency: 137.675MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 5.630ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 7.264ns (frequency: 137.675MHz)
  Total number of paths / destination ports: 5320 / 35
-------------------------------------------------------------------------
Delay:               7.264ns (Levels of Logic = 13)
  Source:            cnt_0 (FF)
  Destination:       cnt_31 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: cnt_0 to cnt_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              5   0.568   1.056  cnt_0 (cnt_0)
     LUT4_L:I0->LO         1   0.439   0.000  Andlut (N22)
     MUXCY:S->O            1   0.298   0.000  Andcy_rn_1 (And_cyo2)
     MUXCY:CI->O           1   0.053   0.000  Andcy_rn_2 (And_cyo3)
     MUXCY:CI->O           1   0.053   0.000  Andcy_rn_3 (And_cyo4)
     MUXCY:CI->O           1   0.053   0.000  norcy_rn_13 (nor_cyo14)
     MUXCY:CI->O           1   0.053   0.000  Andcy_rn_4 (And_cyo5)
     MUXCY:CI->O           1   0.053   0.000  norcy_rn_14 (nor_cyo15)
     MUXCY:CI->O           1   0.053   0.000  norcy_rn_15 (nor_cyo16)
     MUXCY:CI->O           1   0.053   0.000  norcy_rn_16 (nor_cyo17)
     MUXCY:CI->O           1   0.053   0.000  norcy_rn_17 (nor_cyo18)
     MUXCY:CI->O          18   0.942   1.057  GE_stagecy_rn_1 (_n0004)
     LUT4_D:I2->O         18   0.439   1.231  _n0010<13>111_SW0 (N252)
     LUT4_L:I1->LO         1   0.439   0.000  _n0010<24>111 (_n0010<24>)
     FDC:D                     0.370          cnt_24
    ----------------------------------------
    Total                      7.264ns (3.919ns logic, 3.344ns route)
                                       (54.0% logic, 46.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              5.630ns (Levels of Logic = 1)
  Source:            narrow_wide_pulse (FF)
  Destination:       narrow_wide_pulse (PAD)
  Source Clock:      clk rising

  Data Path: narrow_wide_pulse to narrow_wide_pulse
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              2   0.568   0.701  narrow_wide_pulse (narrow_wide_pulse_OBUF)
     OBUF:I->O                 4.361          narrow_wide_pulse_OBUF (narrow_wide_pulse)
    ----------------------------------------
    Total                      5.630ns (4.929ns logic, 0.701ns route)
                                       (87.5% logic, 12.5% route)

=========================================================================
CPU : 6.69 / 7.22 s | Elapsed : 7.00 / 7.00 s
 
--> 

Total memory usage is 104400 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)