test_fifo.vhd

ISE7.1

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-- Company: 
-- Engineer:
--
-- Create Date:   16:37:58 07/06/2007
-- Design Name:   fifo_rs232
-- Module Name:   test_fifo.vhd
-- Project Name:  0705
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: fifo_rs232
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_fifo_vhd IS
END test_fifo_vhd;

ARCHITECTURE behavior OF test_fifo_vhd IS 
--type states is(x_wait,x_generate,w_end)

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT fifo_rs232
	PORT(
		din : IN std_logic_vector(7 downto 0);
		wr_en : IN std_logic;
		wr_clk : IN std_logic;
		rd_en : IN std_logic;
		rd_clk : IN std_logic;
		ainit : IN std_logic;          
		dout : OUT std_logic_vector(7 downto 0);
		full : OUT std_logic;
		empty : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL wr_en :  std_logic := '0';
	SIGNAL wr_clk :  std_logic := '0';
	SIGNAL rd_en :  std_logic := '0';
	SIGNAL rd_clk :  std_logic := '0';
	SIGNAL ainit :  std_logic := '0';
	SIGNAL din :  std_logic_vector(7 downto 0) := (others=>'0');

	--Outputs
	SIGNAL dout :  std_logic_vector(7 downto 0);
	SIGNAL full :  std_logic;
	SIGNAL empty :  std_logic;
	signal cnt:integer;
BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: fifo_rs232 PORT MAP(
		din => din,
		wr_en => wr_en,
		wr_clk => wr_clk,
		rd_en => rd_en,
		rd_clk => rd_clk,
		ainit => ainit,
		dout => dout,
		full => full,
		empty => empty
	);

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;
		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;
aniti_generate:process
               begin
					wait for 20 ns	;
					ainit<='1';
					wait for 20 ns;
					ainit<='0';
					wait;
					end process;
clk_generate:process
             begin
				 wr_clk<='1';
				 rd_clk<='1';
				 wait for 20 ns;
				 wr_clk<='0';
				 rd_clk<='0';
				 wait for 20 ns;
				 end process;
WR_EN_generate:process (wr_clk)
      begin
		if ainit='1' then 
		cnt<=0;
		 elsif rising_edge(wr_clk)then
		    if cnt>=12 then
				      cnt<=0;
						wr_en<='0';
		    elsif cnt>=10 and cnt<=11 then
				    wr_en<='1';
			 else	 
		           cnt<=cnt+1;
       end if;
		 end if;
		end process;
data_in:process(wr_clk)
variable cnt:integer:=0;
        begin
		  if rising_edge(wr_clk) then
			 if cnt>=9 and cnt<10 then
          din<="00000101";
			 elsif cnt=13 then
			     cnt:=0;
          else
			 cnt:=cnt+1;
			 end if;
         end if;
		  end process;

END;