📄 top_fmdm_project.mrp
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Unused block "U_icon_pro/icon_pro/u_icon/u_cmd/u_command_sel/i4/fi/12/u_lut"
(ROM) removed.Unused block "U_icon_pro/icon_pro/u_icon/u_cmd/u_command_sel/i4/fi/13/u_lut"
(ROM) removed.Unused block "U_icon_pro/icon_pro/u_icon/u_cmd/u_command_sel/i4/fi/14/u_lut"
(ROM) removed.Unused block "U_icon_pro/icon_pro/u_icon/u_cmd/u_command_sel/i4/fi/3/u_lut"
(ROM) removed.Unused block "U_icon_pro/icon_pro/u_icon/u_cmd/u_command_sel/i4/fi/6/u_lut"
(ROM) removed.Unused block "U_icon_pro/icon_pro/u_icon/u_cmd/u_command_sel/i4/fi/7/u_lut"
(ROM) removed.Unused block "U_icon_pro/icon_pro/u_icon/u_ctrl_out/f_ncp/0/f_cmd/1/u_hce" (ROM)
removed.Unused block "U_icon_pro/icon_pro/u_icon/u_ctrl_out/f_ncp/0/f_cmd/10/u_hce"
(ROM) removed.Unused block "U_icon_pro/icon_pro/u_icon/u_ctrl_out/f_ncp/0/f_cmd/15/u_hce"
(ROM) removed.Unused block "U_icon_pro/icon_pro/u_icon/u_ctrl_out/f_ncp/0/f_cmd/2/u_hce" (ROM)
removed.Unused block "U_icon_pro/icon_pro/u_icon/u_ctrl_out/f_ncp/0/f_cmd/4/u_hce" (ROM)
removed.Unused block "U_icon_pro/icon_pro/u_icon/u_ctrl_out/f_ncp/0/f_cmd/5/u_hce" (ROM)
removed.Unused block "U_icon_pro/icon_pro/u_icon/u_ctrl_out/f_ncp/0/f_cmd/8/u_hce" (ROM)
removed.Unused block "U_icon_pro/icon_pro/u_icon/u_ctrl_out/f_ncp/0/f_cmd/9/u_hce" (ROM)
removed.Unused block "fifo/BU116" (ROM) removed.Unused block "fifo/BU271" (ROM) removed.Optimized Block(s):TYPE BLOCKGND U_icon_pro/GNDVCC U_icon_pro/VCCLUT4 U_icon_pro/icon_pro/u_icon/u_stat/f_stat/3/u_statLUT3 U_icon_pro/icon_pro/u_icon/u_tdo_mux/i4/fj/1/u_lut3LUT3 U_icon_pro/icon_pro/u_icon/u_tdo_mux/i4/fj/2/u_lut3LUT3 U_icon_pro/icon_pro/u_icon/u_tdo_mux/i4/fj/3/u_lut3LUT3 U_icon_pro/icon_pro/u_icon/u_tdo_mux/i4/fj/4/u_lut3LUT3 U_icon_pro/icon_pro/u_icon/u_tdo_mux/i4/fj/5/u_lut3LUT3 U_icon_pro/icon_pro/u_icon/u_tdo_mux/i4/fj/6/u_lut3GND U_ila_pro_0/GNDVCC U_ila_pro_0/VCCLUT4 U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_stat/f_sstat/7/i_stat/u_statLUT4 U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_stat/f_sstat/8/i_stat/u_statLUT4 U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_stat/f_sstat/9/i_stat/u_statLUT3 U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_stat/u_smux/i5/fj/10/u_lut3LUT3 U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_stat/u_smux/i5/fj/11/u_lut3LUT3 U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_stat/u_smux/i5/fj/12/u_lut3LUT3 U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_stat/u_smux/i5/fj/13/u_lut3LUT3 U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_stat/u_smux/i5/fj/14/u_lut3LUT3 U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_stat/u_smux/i5/fj/15/u_lut3LUT3 U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_stat/u_smux/i5/fj/7/u_lut3GND XST_GNDVCC XST_VCCGND fifo/GNDVCC fifo/VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| adc1_clk | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || adc2_clk | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || adc_log<0> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_log<1> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_log<2> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_log<3> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_log<4> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_log<5> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_log<6> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_log<7> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_log<8> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_log<9> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_log<10> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_log<11> | IOB | INPUT | LVTTL | | | | | || adc_narrow<0> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_narrow<1> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_narrow<2> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_narrow<3> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_narrow<4> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_narrow<5> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_narrow<6> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_narrow<7> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_narrow<8> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_narrow<9> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_narrow<10> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_narrow<11> | IOB | INPUT | LVTTL | | | | | || adc_wide<0> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_wide<1> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_wide<2> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_wide<3> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_wide<4> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_wide<5> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_wide<6> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_wide<7> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_wide<8> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_wide<9> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_wide<10> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || adc_wide<11> | IOB | INPUT | LVTTL | | | | | || clk20mhz | IOB | INPUT | LVTTL | | | | | || delay_in<0> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<1> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<2> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<3> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<4> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<5> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<6> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<7> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<8> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<9> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<10> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<11> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<12> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<13> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<14> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<15> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<16> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<17> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<18> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<19> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || delay_in<20> | IOB | INPUT | LVTTL | | | INFF1 | | IFD || fmdm_select | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || max3232_rec_fpga | IOB | INPUT | LVTTL | | | INFF1 | | IFD || max3232_tr_fpga | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || reset | IOB | INPUT | LVTTL | | | INFF1 | | IFD || test1 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || test3 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || test2<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || test2<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || test2<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || test2<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || test2<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || test2<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || test2<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || test2<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------U_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_ma
tch/pd_rpmU_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/
pd_rpmU_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/
pd_rpmU_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/p
d_rpmU_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_wlcmpce/pd_r
pmU_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_whcmpce/pd_r
pmU_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/pd_rpmU_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scmpce/pd_rp
mU_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpmU_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpmU_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/pd_
rpmU_ila_pro_0/ila_pro_0/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpmSection 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details--------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 74Number of Equivalent Gates for Design = 1,399,113Number of RPM Macros = 12Number of Hard Macros = 0CAPTUREs = 0BSCANs = 1STARTUPs = 0PCILOGICs = 0DCMs = 0GCLKs = 4ICAPs = 018X18 Multipliers = 0Block RAMs = 21TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 491IOB Dual-Rate Flops not driven by LUTs = 0IOB Dual-Rate Flops = 0IOB Slave Pads = 0IOB Master Pads = 0IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 56IOB Flip Flops = 56Unbonded IOBs = 0Bonded IOBs = 74ORCYs = 0XORs = 280CARRY_INITs = 180CARRY_SKIPs = 3CARRY_MUXes = 329Total Shift Registers = 147Static Shift Registers = 83Dynamic Shift Registers = 6416x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MUXFs = 110MULT_ANDs = 04 input LUTs used as Route-Thrus = 2444 input LUTs = 699Slice Latches not driven by LUTs = 8Slice Latches = 8Slice Flip Flops not driven by LUTs = 435Slice Flip Flops = 821Slices = 771F6 Muxes = 22F5 Muxes = 81F8 Muxes = 2F7 Muxes = 5Xilinx Core async_fifo_v6_1, Coregen 7.1.04i = 1Number of LUT signals with 4 loads = 9Number of LUT signals with 3 loads = 5Number of LUT signals with 2 loads = 45Number of LUT signals with 1 load = 611NGM Average fanout of LUT = 1.75NGM Maximum fanout of LUT = 77NGM Average fanin for LUT = 3.1202Number of LUT symbols = 699⌨️ 快捷键说明
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