narrow_wide_pulse_generate.vhd

ISE7.1

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-- Company: 
-- Engineer:
--
-- Create Date:    21:32:52 11/09/06
-- Design Name:    
-- Module Name:    narrow_wide_pulse_generate - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity narrow_wide_pulse_generate is
port(clk:in std_logic;
     reset:in std_logic;
     narrow_wide_pulse:out std_logic);
end narrow_wide_pulse_generate;
architecture Behavioral of narrow_wide_pulse_generate is
type states is(log,narrow,wide);
signal state:states:=log;
	begin
	process(reset,clk)
	variable cnt:integer;
	begin
	if reset='0'then
	   cnt:=0;
		narrow_wide_pulse<='1';
		state<=log;
	elsif(rising_edge(clk))then
			case state is
				when log=>
							if cnt>=102400-1 then ------------对数鉴频3db带宽200MHZ，扫频间隔2M，因此100个数据而每个数据采样1024点。1024*100。
							       cnt:=0;
									 narrow_wide_pulse<='0';	
		                      state<=narrow;
		               else
							       cnt:=cnt+1;
									 state<=log;
                     end if;
            when narrow=>				---------------窄带鉴频一个数据就可以了。
				         if cnt>1023 then
							   cnt:=0;
								narrow_wide_pulse<='1';
								state<=wide;
                      else
							     cnt:=cnt+1;
								  state<=narrow;
                      end if;
            when wide=>
				         if cnt>=20480-1 then --------------暂时定20个频率间隔；
							   cnt:=0;
								narrow_wide_pulse<='0';
								state<=narrow;
                     else
							    cnt:=cnt+1;
								 state<=wide;
                     end if;
        end case;
   end if;
	end process;
	end Behavioral;