test.ant

ISE7.1

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 7.1.04i
--  \   \         Application : ISE Foundation
--  /   /         Filename : test.ant
-- /___/   /\     Timestamp : Mon Jul 16 23:19:58 2007
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: test
--Device: Xilinx
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test IS
END test;

ARCHITECTURE testbench_arch OF test IS
    FILE RESULTS: TEXT OPEN WRITE_MODE IS "F:\vhdlproject\vhdl0716\test.ano";

    COMPONENT narrow_wide_pulse_generate
        PORT (
            clk : In std_logic;
            reset : In std_logic;
            narrow_wide_pulse : Out std_logic
        );
    END COMPONENT;

    SIGNAL clk : std_logic := '0';
    SIGNAL reset : std_logic := '0';
    SIGNAL narrow_wide_pulse : std_logic := '0';

    SHARED VARIABLE TX_ERROR : INTEGER := 0;
    SHARED VARIABLE TX_OUT : LINE;

    constant PERIOD : time := 100 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 0 ns;

    BEGIN
        UUT : narrow_wide_pulse_generate
        PORT MAP (
            clk => clk,
            reset => reset,
            narrow_wide_pulse => narrow_wide_pulse
        );

        PROCESS    -- clock process for clk
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                clk <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                clk <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS    -- Annotation process for clk
            VARIABLE TX_TIME : INTEGER := 0;

            PROCEDURE ANNOTATE_narrow_wide_pulse(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", narrow_wide_pulse, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, narrow_wide_pulse);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
        BEGIN
            WAIT for 1 fs;
            ANNOTATE_narrow_wide_pulse(0);
            WAIT for OFFSET;
            TX_TIME := TX_TIME + 0;
            ANNO_LOOP : LOOP
                --Rising Edge
                WAIT for 65 ns;
                TX_TIME := TX_TIME + 65;
                ANNOTATE_narrow_wide_pulse(TX_TIME);
                WAIT for 35 ns;
                TX_TIME := TX_TIME + 35;
            END LOOP ANNO_LOOP;
        END PROCESS;

        PROCESS
            BEGIN
                -- -------------  Current Time:  235ns
                WAIT FOR 235 ns;
                reset <= '1';
                -- -------------------------------------
                WAIT FOR 1.99999e+007 ns;

                STD.TEXTIO.write(TX_OUT, string'("Total[]"));
                STD.TEXTIO.writeline(RESULTS, TX_OUT);
                ASSERT (FALSE) REPORT
                    "Success! Simulation for annotation completed"
                    SEVERITY FAILURE;
            END PROCESS;

    END testbench_arch;