top_uart.vhd

ISE7.1

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-- Company: 
-- Engineer:
--
-- Create Date:    23:26:10 09/20/06
-- Design Name:    
-- Module Name:    top_uart - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
entity top_uart is
    Port (
	        original_clk        :in std_logic;
           reset               :in std_logic;-----------复位信号
           rxd                 :in std_logic;
           xmit_cmd_p_in       :in std_logic;	  -----设计一计数器计数ENOC.计到512或1024。发送的触发信号
           rec_ready           :out std_logic;
           txd_out             :out std_logic;
           txd_done_out        :out std_logic;
           txdbuf_in           :in std_logic_vector(7 downto 0);
           rec_buf             :out std_logic_vector(7 downto 0);
			  bclk_for_outer      :out std_logic --------------baut率发生器产生的时钟。做FIFO的读时钟。
			  );	 
end top_uart;

architecture Behavioral of top_uart is
  component reciever
           Port ( 
			  bclkr : in std_logic;----采样时钟周期（1个位有16个采样周期）
           resetr : in std_logic;-----复位信号
           rxdr : in std_logic;---串口输入
           r_ready : out std_logic;---接收完成状态输出信号
           rbuf : out std_logic_vector(7 downto 0)---接收缓冲器，或者说是串并转换后的输出信号
			  );
  end component;
  component transfer
           Port ( 
			  bclkt : in std_logic;	------采样时钟
           resett : in std_logic;
           xmit_cmd_p : in std_logic;	----发送启动信号。还是用512计数器的输出做为此启动信号	。应当为一个脉冲信号。
           txdbuf : in std_logic_vector(7 downto 0):="11001010";	 -----发送信号。
           txd : out std_logic;	 -------------发送端口
           txd_done : out std_logic	 ---------	发送完成信号
			        );	
  end component;
  component baud
           	Port ( 
				clk : in std_logic; ---晶振时钟
            resetb : in std_logic;  ---系统复位
            baud_bclk : out std_logic ------采样时钟
				);
  end component;
signal b:std_logic;
	begin
		u_baud:baud port map(
									clk=>original_clk,
									resetb=>reset,
									baud_bclk=>b
									);
		u_reciever:reciever port map(
							            bclkr=>b,
											resetr=>reset,
											rxdr=>rxd,
											r_ready=>rec_ready,
							            rbuf=>rec_buf
											);
	   u_transfer:transfer port map(
											bclkt=>b,
											resett=>reset,
											xmit_cmd_p=>xmit_cmd_p_in,
											txdbuf=>txdbuf_in,
											txd=>txd_out,
											txd_done=>txd_done_out
											);
							bclk_for_outer<=b;

	end Behavioral;