dataformat_adjust_narrowfreq.vhd

ISE7.1

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-- Company: 
-- Engineer:
--
-- Create Date:    16:55:31 01/22/07
-- Design Name:    
-- Module Name:    dataformat_adjust_narrowfreq - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dataformat_adjust_narrowfreq is
port(
     select_clk          :in std_logic;------选择的ADC时钟
     reset               :in std_logic;------------复位脉冲
     en_clk_1024         :in std_logic;  ------求和点数决定的时钟
	  data_in             :in std_logic_vector(21 downto 0);-----累加器的输出
	  dataout_narrowfreq  :out std_logic_vector(7 downto 0);
	  mux_en              :out std_logic
     );
end dataformat_adjust_narrowfreq;

architecture Behavioral of dataformat_adjust_narrowfreq is

type states is(x_wait,adjust,send_data1,send_data2);
signal state:states:=x_wait;
signal data1:std_logic_vector(7 downto 0);-----调整后的寄存器1；
signal data2:std_logic_vector(7 downto 0);-----调整后的寄存器1；
		begin
			process(select_clk,reset)
			begin
				if(rising_edge(select_clk))then
				  if(reset='0')then
				    state<=x_wait;
				  else
					    case state is
						   when x_wait=>
							    if (en_clk_1024='1')then
								    state<=adjust;
								 else 
								    state<=x_wait;mux_en<='0';
								 end if;
					      when adjust=>
							       data1<=data_in(21 downto 14);
							       data2<=data_in(13 downto 6);
									 state<=send_data1;
					      when send_data1=>
							       dataout_narrowfreq<=data1;
							       mux_en<='1';
							       state<=send_data2;
					      when send_data2=>
							       dataout_narrowfreq<=data2;
									 mux_en<='1';
							       state<=x_wait;
					    end case;
				  end if;
				end if;
			end process;
		end 	Behavioral;