top_fmdm_project.vhd

ISE7.1

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-- Company: 
-- Engineer:
--
-- Create Date:    08:18:04 05/08/07
-- Design Name:    
-- Module Name:    top_fmdm_project - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity top_fmdm_project is
port(reset:in std_logic;
     clk20mhz:in std_logic;-------------------------20MHZ晶振输入时钟。
     delay_in :in std_logic_vector(20 downto 0);--总共有21条delay line
	  adc1_clk:out std_logic;-----------------------由FPGA选择的最终的ADC时钟。原理图中ADC_CLK1根ADC_CLK2其实一个冗余。
	  adc2_clk:out std_logic;-----------------------由FPGA选择的最终的ADC时钟。原理图中ADC_CLK1根ADC_CLK2其实一个冗余。
	  adc_log:in std_logic_vector(11 downto 0);-------ADC1
	  adc_wide:in std_logic_vector(11 downto 0);-------ADC2
	  adc_narrow:in std_logic_vector(11 downto 0);-------ADC3
	  max3232_rec_fpga:in std_logic;	--------串口输入。
	  max3232_tr_fpga:out std_logic;	---------串口输出。
     fmdm_select:out std_logic;-------选择射频的脉冲。由FPGA产生。
--	  uart_clk:out std_logic;---------串口的波特率时钟，方便调试。最后要消除
--	  ainit:in std_logic-----------fifo的
     test1:out std_logic ;
	  test2:out std_logic_vector(7 downto 0);
	  test3:  OUT std_logic
	  ) ;
end top_fmdm_project;

architecture Behavioral of top_fmdm_project is
  component narrow_wide_pulse_generate
  port(clk:in std_logic;
     reset:in std_logic;
     narrow_wide_pulse:out std_logic);
  end component;
  component top_uart 
   Port (  original_clk : in std_logic; -----20mhz clk to baud.直接连clk_20mhz
           reset : in std_logic;-----------复位信号，直接连reset
           rxd : in std_logic;		------ RS232's receive serial port直接连
           xmit_cmd_p_in : in std_logic;	  -----发送命令，                                    产生自readfifo_rs232进程	 
           rec_ready : out std_logic; ------------                                             做为时钟选择进程的启动脉冲。
           txd_out : out std_logic;	-------------串口发送端直接连
           txd_done_out : out std_logic; -----发送完成信号，                                   可不用
           txdbuf_in : in std_logic_vector(7 downto 0); -----等待发送的数据,                   由FIFO传入。
           rec_buf : out std_logic_vector(7 downto 0);	----- 接收的数据，给select_clk,以及mux_log_wide_narrow
			  bclk_for_outer:out std_logic); ---------------                                             给fifo的读时钟。
  end component;
  component select_clk Port (
           baud_clk:in std_logic;---晶振时钟 最终考虑到ready信号宽度，决定直接用其
           delay_in :in std_logic_vector(20 downto 0);--总共有21条delay line
			  com_select_clk:in std_logic; ---recready信号做进程敏感信号。即与此信号连	 此信号为高后，根据接收寄存器判断选择哪个clk
			  com_from_serial_receiverrbuf:in std_logic_vector(7 downto 0);----接收到recready后，根据rbuf判断选择哪个clk
			  reset:in std_logic;
           selected_delay_clk:out std_logic-----最终选择的时钟	
			  ) ;
  end component;
  component BUFG
	port
	(
		O : out std_ulogic;
		I : in std_ulogic
	);
  end component;
  component adc_control
   Port (  data_in : in std_logic_vector(11 downto 0);---ADC输入
          data_out_toaccumulator : out std_logic_vector(11 downto 0);----ADC输出至至加法器
          clk : in std_logic;-----ADC输入时钟  与串口中selected_delay对应
			 reset:in std_logic);---系统复位
  end component;
--  component acummulator
--	port (
--	B: IN std_logic_VECTOR(11 downto 0);
--	Q: OUT std_logic_VECTOR(20 downto 0);
--	CLK: IN std_logic;
--	SCLR: IN std_logic);
--  end component;
   component add_accumulator
	port (
	RESET:IN std_logic;
	B: IN std_logic_VECTOR(11 downto 0);
	Q: OUT std_logic_VECTOR(21 downto 0);
	CLK: IN std_logic;
	SCLR: IN std_logic);
   end component;
  component accumulator_ctr_dataadjust
   port(clk:in std_logic;-------adc的时钟，即select_clk选择的时钟
	  accumulator_send_clk:out std_logic;---数据调整,选择发送log,wide,narrow脉冲
	  accumulator_clr_clk:out std_logic	--清零的脉冲。
    );											

  end component;
  component dataformat_adjust_log
   port(select_clk:in std_logic;------选择的ADC时钟
     reset:in std_logic;------------复位脉冲
     en_clk_1024:in std_logic;  ------求和点数决定的时钟
	  data_in:in std_logic_vector(21 downto 0);-----累加器的输出
	  dataout_log:out std_logic_vector(7 downto 0);
	  mux_en:out std_logic
     );
  end component;
  component dataformat_adjust_narrowfreq
   port(select_clk:in std_logic;------选择的ADC时钟
     reset:in std_logic;------------复位脉冲
     en_clk_1024:in std_logic;  ------求和点数决定的时钟
	  data_in:in std_logic_vector(21 downto 0);-----累加器的输出
	  dataout_narrowfreq:out std_logic_vector(7 downto 0);
	  mux_en:out std_logic
     );
  end component;
  component dataformat_adjust_widefreq
   port(select_clk:in std_logic;------选择的ADC时钟
     reset:in std_logic;------------复位脉冲
     en_clk_1024:in std_logic;  ------求和点数决定的时钟
	  data_in:in std_logic_vector(21 downto 0);-----累加器的输出
	  dataout_widefreq:out std_logic_vector(7 downto 0);
	  mux_en:out std_logic
     );
  end component;
  component mux_log_wide_narrow
   port(baudclk:in std_logic;
	  reset:in std_logic;
     mux_en:in std_logic;-----mux的使能,同data_adjust的使能。
	  comm_from_rs232:in std_logic_vector(7 downto 0);-----RS232接收寄存器。
	  ready_rs232:in std_logic;----------------------------RS232接收完毕标志。
     dataout_log:in std_logic_vector(7 downto 0);-----来自鉴频器log输出的数据
	  dataout_widefreq:in std_logic_vector(7 downto 0);---来自鉴频器宽带输出的数据
	  dataout_narrowfreq:in std_logic_vector(7 downto 0);---	来自鉴频器窄带输出的数据
	  dataout_mux:out std_logic_vector(7 downto 0));---mux的输出
  end component;
  component readfifo_RS232
  port(reset:in std_logic;
     rs232_clk_read:in  std_logic;  -----采样EMPTY的时钟	可以用bclk。
     txd_done:in std_logic;
	  fifo_empty:in std_logic;------根据FIFO的空标志，只要非空则可以读，即发送串口发送命令
	  fifo_enable:out std_logic;
	  trans_com:out std_logic-----串口发送命令
     ) ;
  end component;  
--  component fifo_clk_read
--  port(bclk:in std_logic;
--     fifo_read_clk:out std_logic);
--end component;
  component fifo_rs232
   port (
	din: IN std_logic_VECTOR(7 downto 0);
	wr_en: IN std_logic;
	wr_clk: IN std_logic;