transcript

ISE7.1

# Reading D:/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.1e Mar  8 2006 
# //
# //  Copyright 2006 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do test_top_wave_vhd.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity baud
# -- Compiling architecture behavioral of baud
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity reciever
# -- Compiling architecture behavioral of reciever
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity transfer
# -- Compiling architecture behavioral of transfer
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling entity top_uart
# -- Compiling architecture behavioral of top_uart
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity select_clk
# -- Compiling architecture behavioral of select_clk
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity adc_control
# -- Compiling architecture behavioral of adc_control
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity add_accumulator
# -- Compiling architecture behavioral of add_accumulator
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity accumulator_ctr_dataadjust
# -- Compiling architecture behavioral of accumulator_ctr_dataadjust
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity dataformat_adjust_log
# -- Compiling architecture behavioral of dataformat_adjust_log
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity dataformat_adjust_narrowfreq
# -- Compiling architecture behavioral of dataformat_adjust_narrowfreq
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity dataformat_adjust_widefreq
# -- Compiling architecture behavioral of dataformat_adjust_widefreq
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity mux_log_wide_narrow
# -- Compiling architecture behavioral of mux_log_wide_narrow
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_rs232
# -- Compiling architecture fifo_rs232_a of fifo_rs232
# -- Loading entity async_fifo_v6_1
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity readfifo_rs232
# -- Compiling architecture behavioral of readfifo_rs232
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity narrow_wide_pulse_generate
# -- Compiling architecture behavioral of narrow_wide_pulse_generate
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling entity top_fmdm_project
# -- Compiling architecture behavioral of top_fmdm_project
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package numeric_std
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity test_top_wave_vhd
# -- Compiling architecture behavior of test_top_wave_vhd
# ** Warning: test_top_wave.vhd(126): (vcom-1194) FILE declaration was written using 1076-1987 syntax.
# vsim -lib work -t 1ps test_top_wave_vhd 
# Loading d:\win32/../std.standard
# Loading d:\win32/../ieee.std_logic_1164(body)
# Loading d:\win32/../ieee.std_logic_arith(body)
# Loading d:\win32/../ieee.std_logic_unsigned(body)
# Loading d:\win32/../ieee.numeric_std(body)
# Loading d:\win32/../std.textio(body)
# Loading d:\win32/../ieee.std_logic_textio(body)
# Loading work.test_top_wave_vhd(behavior)
# Loading d:\Modeltech_6_1e\xilinx_libs\unisim.vcomponents
# Loading work.top_fmdm_project(behavioral)
# Loading work.top_uart(behavioral)
# Loading work.baud(behavioral)
# Loading work.reciever(behavioral)
# Loading work.transfer(behavioral)
# Loading work.select_clk(behavioral)
# Loading d:\Modeltech_6_1e\xilinx_libs\unisim.bufg(bufg_v)
# Loading work.adc_control(behavioral)
# Loading work.add_accumulator(behavioral)
# Loading work.accumulator_ctr_dataadjust(behavioral)
# Loading work.dataformat_adjust_log(behavioral)
# Loading work.dataformat_adjust_narrowfreq(behavioral)
# Loading work.dataformat_adjust_widefreq(behavioral)
# Loading work.mux_log_wide_narrow(behavioral)
# Loading work.fifo_rs232(fifo_rs232_a)
# Loading d:\Modeltech_6_1e\xilinx_libs\XilinxCoreLib.async_fifo_v6_1(behavioral)
# Loading work.readfifo_rs232(behavioral)
# Loading work.narrow_wide_pulse_generate(behavioral)
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# .main_pane.workspace
# .main_pane.signals.interior.cs
restart
run -all
# Break key hit 
# Break at test_top_wave.vhd line 138