transfer.vhd

ISE7.1

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-- Company: 
-- Engineer:
--
-- Create Date:    11:19:17 09/21/06
-- Design Name:    
-- Module Name:    transfer - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity transfer is
generic(framlent:integer:=8);	----------发送桢长
    Port ( bclkt : in std_logic;	------采样时钟
           resett : in std_logic;
           xmit_cmd_p : in std_logic;	----发送启动信号。还是用512计数器的输出做为此启动信号	。应当为一个脉冲信号。
           txdbuf : in std_logic_vector(7 downto 0);	 -----发送信号。
           txd : out std_logic;	 -------------发送端口
           txd_done : out std_logic);	---------	发送完成信号
end transfer;

architecture Behavioral of transfer is
type states is(x_idle,x_start,x_wait,x_shift,x_stop);
signal state:states:=x_idle;

	begin
		process(bclkt,resett,xmit_cmd_p,txdbuf)
		variable xcnt16:std_logic_vector(4 downto 0):="00000"; -----使之成为为一个真实发送信号
		variable xbitcnt:integer:=0;----为了移位以及判断发送是否完成而设置的
		variable txds:std_logic;
		begin
					if resett='0'then 
					      state<=x_idle;
							txd_done<='0';
							txds:='1';
							xcnt16:=(others=>'0');
							xbitcnt:=0;
					      txd<='1';  
					elsif rising_edge(bclkt)then 
					  	case state is
								when x_idle=> 
										txd_done<='0';
									   if xmit_cmd_p='1'then 
										state<=x_start;
										else 
										state<=x_idle;
										end if;
						      when x_start=>
									   txd_done<='0';
										if xcnt16>="01111"then 
										state<=x_wait;
										xcnt16:="00000"; 
										else 
										xcnt16:=xcnt16+1;
										txds:='0';	
										state<=x_start;	  --使0延续一个比特
										end if;														
								when x_wait=>
									   txd_done<='0';
										if xcnt16>="01110"then
											  if xbitcnt=framlent then 
												state<=x_stop;
												xbitcnt:=0;
											  else 
											   state<=x_shift;	
											  end if;
									     	  xcnt16:="00000";
										else 
											xcnt16:=xcnt16+1;
										   state<=x_wait;
										end if;
								when x_shift=>
								        txds:=txdbuf(xbitcnt);
										  xbitcnt:=xbitcnt+1;
										  txd_done<='0';
										  state<=x_wait;
								when x_stop=>
									if xcnt16>="01111"then
										if xmit_cmd_p='0'then 
											state<=x_idle;
											xcnt16:="00000";
											txd_done<='0';
										else 
											xcnt16:=xcnt16;
											state<=x_stop;
										end if;
											txd_done<='1';
									else 
										   xcnt16:=xcnt16+1;
											txds:='1';
											state<=x_stop;
								  end if;
								when	others=>
								        state<=x_idle;
						end case;
				 end if;
				  txd<=txds;
	 end process;
	end Behavioral;