test_top_wave.vhd

ISE7.1

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-- Company: 
-- Engineer:
--
-- Create Date:   09:15:36 05/09/2007
-- Design Name:   top_fmdm_project
-- Module Name:   test_top_wave.vhd
-- Project Name:  fmdm_modified
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: top_fmdm_project
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use STD.TEXTIO.ALL;
USE ieee.std_logic_textio.all;

ENTITY test_top_wave_vhd IS
END test_top_wave_vhd;

ARCHITECTURE behavior OF test_top_wave_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT top_fmdm_project
	PORT(
		reset : IN std_logic;
		clk20mhz : IN std_logic;
		delay_in : IN std_logic_vector(20 downto 0);
		adc_log : IN std_logic_vector(11 downto 0);
		adc_wide : IN std_logic_vector(11 downto 0);
		adc_narrow : IN std_logic_vector(11 downto 0);
		max3232_rec_fpga : IN std_logic;          
		adc1_clk : OUT std_logic;
		adc2_clk : OUT std_logic;
		max3232_tr_fpga : OUT std_logic;
		fmdm_select : OUT std_logic;
		test1 : OUT std_logic;
		test2 : OUT std_logic_vector(7 downto 0);
		test3:  OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL reset :  std_logic := '0';
	SIGNAL clk20mhz :  std_logic := '0';
	SIGNAL max3232_rec_fpga :  std_logic := '1';
	SIGNAL delay_in :  std_logic_vector(20 downto 0) := (others=>'0');
	SIGNAL adc_log :  std_logic_vector(11 downto 0) := (others=>'0');
	SIGNAL adc_wide :  std_logic_vector(11 downto 0) := (others=>'0');
	SIGNAL adc_narrow :  std_logic_vector(11 downto 0) := (others=>'0');
	signal baud_bclk:  std_logic := '0';
	signal cnt: integer;

	--Outputs
	SIGNAL adc1_clk :  std_logic;
	SIGNAL adc2_clk :  std_logic;
	SIGNAL max3232_tr_fpga :  std_logic;
	SIGNAL fmdm_select :  std_logic;
	SIGNAL test1 :  std_logic;
	SIGNAL test2 :  std_logic_vector(7 downto 0);
	SIGNAL test3:   std_logic;



BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: top_fmdm_project PORT MAP(
		reset => reset,
		clk20mhz => clk20mhz,
		delay_in => delay_in,
		adc1_clk => adc1_clk,
		adc2_clk => adc2_clk,
		adc_log => adc_log,
		adc_wide => adc_wide,
		adc_narrow => adc_narrow,
		max3232_rec_fpga => max3232_rec_fpga,
		max3232_tr_fpga => max3232_tr_fpga,
		fmdm_select => fmdm_select,
		test1 => test1,
		test2 => test2,
		test3 => test3
	);

	restart: PROCESS		  ----复位
	BEGIN
		wait for 100 ns;
		reset<='1';
		wait;
	END PROCESS;
clk_20mhz_generate:process		----20mhz脉冲产生
                   begin
						 clk20mhz<='1';
						 wait for 25 ns;
						 clk20mhz<='0';
						 wait for 25 ns;
                   end process;

delay0_generate:		 ---仅产生了0路延迟信号
              process
				  begin
				  delay_in(0)<='1';
				  wait for  333 ns;
				  delay_in(0)<='0';
				  wait for 333 ns;
				  end process;
adclog:process	(adc1_clk)----读AD信号
       file data_file:TEXT is in " sin_data_bit.txt"; 
       variable li:LINE;
       variable adc_log_buf:std_logic_vector(11 downto 0):="000000000000";
       begin
		 if rising_edge(adc1_clk)then
		    if not endfile(data_file)	then
				readline(data_file,li);
		      read(li,adc_log_buf);
				adc_log<=adc_log_buf;
			 end if;
       end if;
		end process;
baud_clk_generate: process(clk20mhz,reset )
	          variable cnt:integer:=0;
	            begin
	            if rising_edge(clk20mhz)then
	              if reset='0' then cnt:=0;baud_bclk<='0'; 
	              elsif cnt>=33 then cnt:=0;baud_bclk<='1';	 ------20mhz分频到38400约521	除以采样频率16  约等于33
	            else cnt:=cnt+1;baud_bclk<='0';
	              end if;
               end if;
	           end	  process;
command_receive:
                process(baud_bclk,reset)
					 begin
					 if reset='0' then
					  cnt<=1;
					 elsif rising_edge(baud_bclk)	 then
					    if cnt=32 then 
						 cnt<=1;
						 else cnt<=cnt+1;
						 end if;
                end if;
					 end process;

					 process(baud_bclk,reset)
					 begin
					    if reset='0' then 
					 	     max3232_rec_fpga <= '1';
                   elsif rising_edge(baud_bclk) then
						     if cnt<16*8 then max3232_rec_fpga <='0';
							  elsif (cnt>=16*8 and cnt<16*11)then 
							  max3232_rec_fpga <='1';
							  elsif (cnt>=16*11 and cnt<16*17)then
							  max3232_rec_fpga <='0';
							  elsif (cnt>=16*17 and cnt<16*18)then
                       max3232_rec_fpga <='1';
							  end if;
                    end if;
				  	 end process;


END;