add_accumulator.vhd

ISE7.1

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-- Company: 
-- Engineer:
--
-- Create Date:    18:27:45 05/30/07
-- Design Name:    
-- Module Name:    add_accumulator - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity add_accumulator is
	port (
	RESET        :IN std_logic;
	B            :IN std_logic_VECTOR(11 downto 0);
	Q            :OUT std_logic_VECTOR(21 downto 0);
	CLK          :IN std_logic;
	SCLR         :IN std_logic
	     );
end add_accumulator;

architecture Behavioral of add_accumulator is
signal q_buf: std_logic_VECTOR(21 downto 0):=(others=>'0');

	begin
		process(CLK,RESET,SCLR,B)
		variable cnt:integer:=0;
		begin
		   if RESET='0' THEN
		        q_buf<=(others=>'0');
				  Q<=(others=>'0');
		   elsif rising_edge(CLK)	THEN
		        if SCLR='1' THEN 
				     q_buf<=(others=>'0');
		           Q<=(others=>'0');
		        else
		    		  q_buf<=q_buf+B;
		        end if;
				  Q<=q_buf;
		   end if;
		end process;

	end Behavioral;